From: Ju-Zhe Zhong Date: Tue, 31 Jan 2023 12:55:37 +0000 (+0800) Subject: RISC-V: Add vand.vv C++ API tests X-Git-Tag: basepoints/gcc-14~1608 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=768a8952539ca7dfb6a61f17595fa9f6ea1f27b2;p=thirdparty%2Fgcc.git RISC-V: Add vand.vv C++ API tests gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/vand_vv-1.C: New test. * g++.target/riscv/rvv/base/vand_vv-2.C: New test. * g++.target/riscv/rvv/base/vand_vv-3.C: New test. * g++.target/riscv/rvv/base/vand_vv_mu-1.C: New test. * g++.target/riscv/rvv/base/vand_vv_mu-2.C: New test. * g++.target/riscv/rvv/base/vand_vv_mu-3.C: New test. * g++.target/riscv/rvv/base/vand_vv_tu-1.C: New test. * g++.target/riscv/rvv/base/vand_vv_tu-2.C: New test. * g++.target/riscv/rvv/base/vand_vv_tu-3.C: New test. * g++.target/riscv/rvv/base/vand_vv_tum-1.C: New test. * g++.target/riscv/rvv/base/vand_vv_tum-2.C: New test. * g++.target/riscv/rvv/base/vand_vv_tum-3.C: New test. * g++.target/riscv/rvv/base/vand_vv_tumu-1.C: New test. * g++.target/riscv/rvv/base/vand_vv_tumu-2.C: New test. * g++.target/riscv/rvv/base/vand_vv_tumu-3.C: New test. * g++.target/riscv/rvv/base/vsub_vv-1.C: New test. * g++.target/riscv/rvv/base/vsub_vv-2.C: New test. * g++.target/riscv/rvv/base/vsub_vv-3.C: New test. * g++.target/riscv/rvv/base/vsub_vv_mu-1.C: New test. * g++.target/riscv/rvv/base/vsub_vv_mu-2.C: New test. * g++.target/riscv/rvv/base/vsub_vv_mu-3.C: New test. * g++.target/riscv/rvv/base/vsub_vv_tu-1.C: New test. * g++.target/riscv/rvv/base/vsub_vv_tu-2.C: New test. * g++.target/riscv/rvv/base/vsub_vv_tu-3.C: New test. * g++.target/riscv/rvv/base/vsub_vv_tum-1.C: New test. * g++.target/riscv/rvv/base/vsub_vv_tum-2.C: New test. * g++.target/riscv/rvv/base/vsub_vv_tum-3.C: New test. * g++.target/riscv/rvv/base/vsub_vv_tumu-1.C: New test. * g++.target/riscv/rvv/base/vsub_vv_tumu-2.C: New test. * g++.target/riscv/rvv/base/vsub_vv_tumu-3.C: New test. --- diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vand_vv-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vv-1.C new file mode 100644 index 000000000000..f229e55d6d15 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vv-1.C @@ -0,0 +1,578 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vand(vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint8mf4_t test___riscv_vand(vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint8mf2_t test___riscv_vand(vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint8m1_t test___riscv_vand(vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint8m2_t test___riscv_vand(vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint8m4_t test___riscv_vand(vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint8m8_t test___riscv_vand(vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint16mf4_t test___riscv_vand(vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint16mf2_t test___riscv_vand(vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint16m1_t test___riscv_vand(vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint16m2_t test___riscv_vand(vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint16m4_t test___riscv_vand(vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint16m8_t test___riscv_vand(vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint32mf2_t test___riscv_vand(vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint32m1_t test___riscv_vand(vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint32m2_t test___riscv_vand(vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint32m4_t test___riscv_vand(vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint32m8_t test___riscv_vand(vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint64m1_t test___riscv_vand(vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint64m2_t test___riscv_vand(vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint64m4_t test___riscv_vand(vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint64m8_t test___riscv_vand(vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vand(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vand(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vand(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint8m1_t test___riscv_vand(vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint8m2_t test___riscv_vand(vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint8m4_t test___riscv_vand(vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint8m8_t test___riscv_vand(vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vand(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vand(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint16m1_t test___riscv_vand(vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint16m2_t test___riscv_vand(vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint16m4_t test___riscv_vand(vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint16m8_t test___riscv_vand(vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vand(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint32m1_t test___riscv_vand(vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint32m2_t test___riscv_vand(vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint32m4_t test___riscv_vand(vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint32m8_t test___riscv_vand(vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint64m1_t test___riscv_vand(vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint64m2_t test___riscv_vand(vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint64m4_t test___riscv_vand(vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint64m8_t test___riscv_vand(vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint8mf8_t test___riscv_vand(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vand(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vand(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint8m1_t test___riscv_vand(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint8m2_t test___riscv_vand(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint8m4_t test___riscv_vand(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint8m8_t test___riscv_vand(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vand(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vand(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint16m1_t test___riscv_vand(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint16m2_t test___riscv_vand(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint16m4_t test___riscv_vand(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint16m8_t test___riscv_vand(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vand(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint32m1_t test___riscv_vand(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint32m2_t test___riscv_vand(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint32m4_t test___riscv_vand(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint32m8_t test___riscv_vand(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint64m1_t test___riscv_vand(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint64m2_t test___riscv_vand(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint64m4_t test___riscv_vand(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint64m8_t test___riscv_vand(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vand(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vand(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vand(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vand(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vand(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vand(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vand(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vand(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vand(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vand(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vand(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vand(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vand(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vand(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vand(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vand(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vand(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vand(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vand(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vand(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vand(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vand(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vand_vv-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vv-2.C new file mode 100644 index 000000000000..d538f3e842b8 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vv-2.C @@ -0,0 +1,578 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vand(vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint8mf4_t test___riscv_vand(vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint8mf2_t test___riscv_vand(vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint8m1_t test___riscv_vand(vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint8m2_t test___riscv_vand(vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint8m4_t test___riscv_vand(vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint8m8_t test___riscv_vand(vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint16mf4_t test___riscv_vand(vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint16mf2_t test___riscv_vand(vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint16m1_t test___riscv_vand(vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint16m2_t test___riscv_vand(vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint16m4_t test___riscv_vand(vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint16m8_t test___riscv_vand(vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint32mf2_t test___riscv_vand(vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint32m1_t test___riscv_vand(vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint32m2_t test___riscv_vand(vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint32m4_t test___riscv_vand(vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint32m8_t test___riscv_vand(vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint64m1_t test___riscv_vand(vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint64m2_t test___riscv_vand(vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint64m4_t test___riscv_vand(vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint64m8_t test___riscv_vand(vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint8mf8_t test___riscv_vand(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint8mf4_t test___riscv_vand(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint8mf2_t test___riscv_vand(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint8m1_t test___riscv_vand(vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint8m2_t test___riscv_vand(vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint8m4_t test___riscv_vand(vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint8m8_t test___riscv_vand(vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint16mf4_t test___riscv_vand(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint16mf2_t test___riscv_vand(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint16m1_t test___riscv_vand(vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint16m2_t test___riscv_vand(vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint16m4_t test___riscv_vand(vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint16m8_t test___riscv_vand(vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint32mf2_t test___riscv_vand(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint32m1_t test___riscv_vand(vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint32m2_t test___riscv_vand(vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint32m4_t test___riscv_vand(vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint32m8_t test___riscv_vand(vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint64m1_t test___riscv_vand(vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint64m2_t test___riscv_vand(vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint64m4_t test___riscv_vand(vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint64m8_t test___riscv_vand(vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint8mf8_t test___riscv_vand(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint8mf4_t test___riscv_vand(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint8mf2_t test___riscv_vand(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint8m1_t test___riscv_vand(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint8m2_t test___riscv_vand(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint8m4_t test___riscv_vand(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint8m8_t test___riscv_vand(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint16mf4_t test___riscv_vand(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint16mf2_t test___riscv_vand(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint16m1_t test___riscv_vand(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint16m2_t test___riscv_vand(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint16m4_t test___riscv_vand(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint16m8_t test___riscv_vand(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint32mf2_t test___riscv_vand(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint32m1_t test___riscv_vand(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint32m2_t test___riscv_vand(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint32m4_t test___riscv_vand(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint32m8_t test___riscv_vand(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint64m1_t test___riscv_vand(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint64m2_t test___riscv_vand(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint64m4_t test___riscv_vand(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint64m8_t test___riscv_vand(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vand(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vand(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vand(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint8m1_t test___riscv_vand(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint8m2_t test___riscv_vand(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint8m4_t test___riscv_vand(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint8m8_t test___riscv_vand(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vand(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vand(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint16m1_t test___riscv_vand(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint16m2_t test___riscv_vand(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint16m4_t test___riscv_vand(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint16m8_t test___riscv_vand(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vand(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint32m1_t test___riscv_vand(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint32m2_t test___riscv_vand(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint32m4_t test___riscv_vand(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint32m8_t test___riscv_vand(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint64m1_t test___riscv_vand(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint64m2_t test___riscv_vand(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint64m4_t test___riscv_vand(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint64m8_t test___riscv_vand(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vand_vv-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vv-3.C new file mode 100644 index 000000000000..56597b83db04 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vv-3.C @@ -0,0 +1,578 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vand(vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint8mf4_t test___riscv_vand(vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint8mf2_t test___riscv_vand(vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint8m1_t test___riscv_vand(vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint8m2_t test___riscv_vand(vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint8m4_t test___riscv_vand(vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint8m8_t test___riscv_vand(vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint16mf4_t test___riscv_vand(vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint16mf2_t test___riscv_vand(vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint16m1_t test___riscv_vand(vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint16m2_t test___riscv_vand(vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint16m4_t test___riscv_vand(vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint16m8_t test___riscv_vand(vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint32mf2_t test___riscv_vand(vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint32m1_t test___riscv_vand(vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint32m2_t test___riscv_vand(vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint32m4_t test___riscv_vand(vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint32m8_t test___riscv_vand(vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint64m1_t test___riscv_vand(vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint64m2_t test___riscv_vand(vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint64m4_t test___riscv_vand(vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint64m8_t test___riscv_vand(vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint8mf8_t test___riscv_vand(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint8mf4_t test___riscv_vand(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint8mf2_t test___riscv_vand(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint8m1_t test___riscv_vand(vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint8m2_t test___riscv_vand(vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint8m4_t test___riscv_vand(vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint8m8_t test___riscv_vand(vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint16mf4_t test___riscv_vand(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint16mf2_t test___riscv_vand(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint16m1_t test___riscv_vand(vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint16m2_t test___riscv_vand(vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint16m4_t test___riscv_vand(vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint16m8_t test___riscv_vand(vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint32mf2_t test___riscv_vand(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint32m1_t test___riscv_vand(vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint32m2_t test___riscv_vand(vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint32m4_t test___riscv_vand(vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint32m8_t test___riscv_vand(vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint64m1_t test___riscv_vand(vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint64m2_t test___riscv_vand(vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint64m4_t test___riscv_vand(vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint64m8_t test___riscv_vand(vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint8mf8_t test___riscv_vand(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint8mf4_t test___riscv_vand(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint8mf2_t test___riscv_vand(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint8m1_t test___riscv_vand(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint8m2_t test___riscv_vand(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint8m4_t test___riscv_vand(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint8m8_t test___riscv_vand(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint16mf4_t test___riscv_vand(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint16mf2_t test___riscv_vand(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint16m1_t test___riscv_vand(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint16m2_t test___riscv_vand(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint16m4_t test___riscv_vand(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint16m8_t test___riscv_vand(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint32mf2_t test___riscv_vand(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint32m1_t test___riscv_vand(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint32m2_t test___riscv_vand(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint32m4_t test___riscv_vand(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint32m8_t test___riscv_vand(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint64m1_t test___riscv_vand(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint64m2_t test___riscv_vand(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint64m4_t test___riscv_vand(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint64m8_t test___riscv_vand(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vand(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vand(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vand(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint8m1_t test___riscv_vand(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint8m2_t test___riscv_vand(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint8m4_t test___riscv_vand(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint8m8_t test___riscv_vand(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vand(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vand(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint16m1_t test___riscv_vand(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint16m2_t test___riscv_vand(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint16m4_t test___riscv_vand(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint16m8_t test___riscv_vand(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vand(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint32m1_t test___riscv_vand(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint32m2_t test___riscv_vand(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint32m4_t test___riscv_vand(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint32m8_t test___riscv_vand(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint64m1_t test___riscv_vand(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint64m2_t test___riscv_vand(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint64m4_t test___riscv_vand(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint64m8_t test___riscv_vand(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_mu-1.C new file mode 100644 index 000000000000..bd969f72f405 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_mu-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vand_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vand_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vand_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vand_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vand_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vand_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vand_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vand_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vand_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vand_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vand_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vand_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vand_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vand_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vand_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vand_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vand_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vand_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vand_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vand_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vand_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vand_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vand_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vand_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vand_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vand_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vand_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vand_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vand_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vand_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vand_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vand_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vand_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vand_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vand_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vand_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vand_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vand_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vand_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vand_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vand_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vand_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vand_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vand_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_mu-2.C new file mode 100644 index 000000000000..5b63c72d0d4c --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_mu-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vand_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vand_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vand_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vand_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vand_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vand_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vand_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vand_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vand_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vand_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vand_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vand_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vand_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vand_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vand_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vand_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vand_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vand_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vand_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vand_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vand_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vand_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vand_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vand_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vand_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vand_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vand_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vand_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vand_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vand_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vand_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vand_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vand_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vand_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vand_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vand_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vand_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vand_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vand_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vand_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vand_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vand_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vand_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vand_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_mu-3.C new file mode 100644 index 000000000000..236c7ee12037 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_mu-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vand_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vand_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vand_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vand_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vand_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vand_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vand_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vand_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vand_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vand_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vand_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vand_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vand_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vand_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vand_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vand_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vand_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vand_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vand_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vand_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vand_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vand_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vand_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vand_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vand_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vand_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vand_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vand_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vand_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vand_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vand_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vand_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vand_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vand_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vand_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vand_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vand_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vand_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vand_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vand_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vand_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vand_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vand_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vand_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_tu-1.C new file mode 100644 index 000000000000..0e6b84d5dbb2 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_tu-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vand_tu(vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vand_tu(vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vand_tu(vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vand_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vand_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vand_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vand_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vand_tu(vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vand_tu(vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vand_tu(vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vand_tu(vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vand_tu(vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vand_tu(vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vand_tu(vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vand_tu(vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vand_tu(vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vand_tu(vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vand_tu(vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vand_tu(vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vand_tu(vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vand_tu(vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vand_tu(vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vand_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vand_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vand_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vand_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vand_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vand_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vand_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vand_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vand_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vand_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vand_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vand_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vand_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vand_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vand_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vand_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vand_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vand_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vand_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vand_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vand_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vand_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_tu-2.C new file mode 100644 index 000000000000..6a6a81587665 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_tu-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vand_tu(vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vand_tu(vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vand_tu(vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vand_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vand_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vand_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vand_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vand_tu(vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vand_tu(vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vand_tu(vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vand_tu(vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vand_tu(vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vand_tu(vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vand_tu(vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vand_tu(vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vand_tu(vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vand_tu(vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vand_tu(vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vand_tu(vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vand_tu(vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vand_tu(vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vand_tu(vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vand_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vand_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vand_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vand_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vand_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vand_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vand_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vand_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vand_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vand_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vand_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vand_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vand_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vand_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vand_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vand_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vand_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vand_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vand_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vand_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vand_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vand_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_tu-3.C new file mode 100644 index 000000000000..af641afae3c3 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_tu-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vand_tu(vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vand_tu(vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vand_tu(vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vand_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vand_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vand_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vand_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vand_tu(vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vand_tu(vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vand_tu(vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vand_tu(vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vand_tu(vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vand_tu(vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vand_tu(vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vand_tu(vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vand_tu(vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vand_tu(vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vand_tu(vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vand_tu(vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vand_tu(vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vand_tu(vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vand_tu(vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vand_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vand_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vand_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vand_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vand_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vand_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vand_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vand_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vand_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vand_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vand_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vand_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vand_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vand_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vand_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vand_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vand_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vand_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vand_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vand_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vand_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vand_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_tum-1.C new file mode 100644 index 000000000000..c462026cf1a0 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_tum-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vand_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vand_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vand_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vand_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vand_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vand_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vand_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vand_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vand_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vand_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vand_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vand_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vand_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vand_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vand_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vand_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vand_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vand_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vand_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vand_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vand_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vand_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vand_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vand_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vand_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vand_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vand_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vand_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vand_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vand_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vand_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vand_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vand_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vand_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vand_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vand_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vand_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vand_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vand_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vand_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vand_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vand_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vand_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vand_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_tum-2.C new file mode 100644 index 000000000000..511396994d20 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_tum-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vand_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vand_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vand_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vand_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vand_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vand_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vand_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vand_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vand_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vand_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vand_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vand_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vand_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vand_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vand_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vand_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vand_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vand_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vand_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vand_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vand_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vand_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vand_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vand_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vand_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vand_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vand_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vand_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vand_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vand_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vand_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vand_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vand_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vand_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vand_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vand_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vand_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vand_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vand_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vand_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vand_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vand_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vand_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vand_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_tum-3.C new file mode 100644 index 000000000000..f8d7d8edc3d9 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_tum-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vand_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vand_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vand_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vand_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vand_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vand_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vand_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vand_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vand_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vand_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vand_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vand_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vand_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vand_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vand_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vand_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vand_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vand_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vand_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vand_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vand_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vand_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vand_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vand_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vand_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vand_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vand_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vand_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vand_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vand_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vand_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vand_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vand_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vand_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vand_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vand_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vand_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vand_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vand_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vand_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vand_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vand_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vand_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vand_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_tumu-1.C new file mode 100644 index 000000000000..9e32e1ef995e --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_tumu-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vand_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vand_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vand_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vand_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vand_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vand_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vand_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vand_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vand_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vand_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vand_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vand_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vand_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vand_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vand_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vand_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vand_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vand_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vand_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vand_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vand_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vand_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vand_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vand_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vand_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vand_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vand_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vand_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vand_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vand_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vand_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vand_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vand_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vand_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vand_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vand_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vand_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vand_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vand_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vand_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vand_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vand_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vand_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vand_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_tumu-2.C new file mode 100644 index 000000000000..e4b043aee09f --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_tumu-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vand_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vand_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vand_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vand_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vand_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vand_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vand_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vand_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vand_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vand_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vand_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vand_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vand_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vand_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vand_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vand_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vand_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vand_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vand_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vand_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vand_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vand_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vand_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vand_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vand_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vand_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vand_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vand_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vand_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vand_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vand_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vand_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vand_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vand_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vand_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vand_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vand_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vand_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vand_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vand_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vand_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vand_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vand_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vand_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_tumu-3.C new file mode 100644 index 000000000000..3694fa97375a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_tumu-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vand_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vand_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vand_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vand_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vand_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vand_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vand_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vand_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vand_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vand_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vand_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vand_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vand_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vand_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vand_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vand_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vand_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vand_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vand_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vand_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vand_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vand_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vand_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vand_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vand_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vand_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vand_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vand_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vand_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vand_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vand_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vand_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vand_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vand_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vand_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vand_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vand_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vand_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vand_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vand_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vand_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vand_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vand_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vand_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv-1.C new file mode 100644 index 000000000000..958be6f5c829 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv-1.C @@ -0,0 +1,578 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsub(vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint8mf4_t test___riscv_vsub(vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint8mf2_t test___riscv_vsub(vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint8m1_t test___riscv_vsub(vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint8m2_t test___riscv_vsub(vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint8m4_t test___riscv_vsub(vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint8m8_t test___riscv_vsub(vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint16mf4_t test___riscv_vsub(vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint16mf2_t test___riscv_vsub(vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint16m1_t test___riscv_vsub(vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint16m2_t test___riscv_vsub(vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint16m4_t test___riscv_vsub(vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint16m8_t test___riscv_vsub(vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint32mf2_t test___riscv_vsub(vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint32m1_t test___riscv_vsub(vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint32m2_t test___riscv_vsub(vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint32m4_t test___riscv_vsub(vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint32m8_t test___riscv_vsub(vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint64m1_t test___riscv_vsub(vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint64m2_t test___riscv_vsub(vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint64m4_t test___riscv_vsub(vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint64m8_t test___riscv_vsub(vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vsub(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vsub(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vsub(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint8m1_t test___riscv_vsub(vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint8m2_t test___riscv_vsub(vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint8m4_t test___riscv_vsub(vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint8m8_t test___riscv_vsub(vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vsub(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vsub(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint16m1_t test___riscv_vsub(vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint16m2_t test___riscv_vsub(vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint16m4_t test___riscv_vsub(vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint16m8_t test___riscv_vsub(vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vsub(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint32m1_t test___riscv_vsub(vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint32m2_t test___riscv_vsub(vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint32m4_t test___riscv_vsub(vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint32m8_t test___riscv_vsub(vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint64m1_t test___riscv_vsub(vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint64m2_t test___riscv_vsub(vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint64m4_t test___riscv_vsub(vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint64m8_t test___riscv_vsub(vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint8mf8_t test___riscv_vsub(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vsub(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vsub(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint8m1_t test___riscv_vsub(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint8m2_t test___riscv_vsub(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint8m4_t test___riscv_vsub(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint8m8_t test___riscv_vsub(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vsub(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vsub(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint16m1_t test___riscv_vsub(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint16m2_t test___riscv_vsub(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint16m4_t test___riscv_vsub(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint16m8_t test___riscv_vsub(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vsub(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint32m1_t test___riscv_vsub(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint32m2_t test___riscv_vsub(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint32m4_t test___riscv_vsub(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint32m8_t test___riscv_vsub(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint64m1_t test___riscv_vsub(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint64m2_t test___riscv_vsub(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint64m4_t test___riscv_vsub(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint64m8_t test___riscv_vsub(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vsub(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vsub(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vsub(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vsub(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vsub(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vsub(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vsub(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vsub(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vsub(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vsub(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vsub(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vsub(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vsub(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vsub(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vsub(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vsub(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vsub(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vsub(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vsub(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vsub(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vsub(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vsub(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv-2.C new file mode 100644 index 000000000000..3aa6a916405c --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv-2.C @@ -0,0 +1,578 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsub(vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint8mf4_t test___riscv_vsub(vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint8mf2_t test___riscv_vsub(vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint8m1_t test___riscv_vsub(vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint8m2_t test___riscv_vsub(vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint8m4_t test___riscv_vsub(vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint8m8_t test___riscv_vsub(vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint16mf4_t test___riscv_vsub(vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint16mf2_t test___riscv_vsub(vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint16m1_t test___riscv_vsub(vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint16m2_t test___riscv_vsub(vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint16m4_t test___riscv_vsub(vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint16m8_t test___riscv_vsub(vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint32mf2_t test___riscv_vsub(vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint32m1_t test___riscv_vsub(vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint32m2_t test___riscv_vsub(vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint32m4_t test___riscv_vsub(vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint32m8_t test___riscv_vsub(vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint64m1_t test___riscv_vsub(vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint64m2_t test___riscv_vsub(vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint64m4_t test___riscv_vsub(vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint64m8_t test___riscv_vsub(vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint8mf8_t test___riscv_vsub(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint8mf4_t test___riscv_vsub(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint8mf2_t test___riscv_vsub(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint8m1_t test___riscv_vsub(vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint8m2_t test___riscv_vsub(vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint8m4_t test___riscv_vsub(vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint8m8_t test___riscv_vsub(vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint16mf4_t test___riscv_vsub(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint16mf2_t test___riscv_vsub(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint16m1_t test___riscv_vsub(vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint16m2_t test___riscv_vsub(vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint16m4_t test___riscv_vsub(vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint16m8_t test___riscv_vsub(vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint32mf2_t test___riscv_vsub(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint32m1_t test___riscv_vsub(vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint32m2_t test___riscv_vsub(vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint32m4_t test___riscv_vsub(vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint32m8_t test___riscv_vsub(vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint64m1_t test___riscv_vsub(vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint64m2_t test___riscv_vsub(vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint64m4_t test___riscv_vsub(vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint64m8_t test___riscv_vsub(vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint8mf8_t test___riscv_vsub(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint8mf4_t test___riscv_vsub(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint8mf2_t test___riscv_vsub(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint8m1_t test___riscv_vsub(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint8m2_t test___riscv_vsub(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint8m4_t test___riscv_vsub(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint8m8_t test___riscv_vsub(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint16mf4_t test___riscv_vsub(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint16mf2_t test___riscv_vsub(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint16m1_t test___riscv_vsub(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint16m2_t test___riscv_vsub(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint16m4_t test___riscv_vsub(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint16m8_t test___riscv_vsub(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint32mf2_t test___riscv_vsub(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint32m1_t test___riscv_vsub(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint32m2_t test___riscv_vsub(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint32m4_t test___riscv_vsub(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint32m8_t test___riscv_vsub(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint64m1_t test___riscv_vsub(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint64m2_t test___riscv_vsub(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint64m4_t test___riscv_vsub(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint64m8_t test___riscv_vsub(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vsub(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vsub(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vsub(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint8m1_t test___riscv_vsub(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint8m2_t test___riscv_vsub(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint8m4_t test___riscv_vsub(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint8m8_t test___riscv_vsub(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vsub(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vsub(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint16m1_t test___riscv_vsub(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint16m2_t test___riscv_vsub(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint16m4_t test___riscv_vsub(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint16m8_t test___riscv_vsub(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vsub(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint32m1_t test___riscv_vsub(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint32m2_t test___riscv_vsub(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint32m4_t test___riscv_vsub(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint32m8_t test___riscv_vsub(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint64m1_t test___riscv_vsub(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint64m2_t test___riscv_vsub(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint64m4_t test___riscv_vsub(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint64m8_t test___riscv_vsub(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv-3.C new file mode 100644 index 000000000000..9c755e1463cc --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv-3.C @@ -0,0 +1,578 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsub(vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint8mf4_t test___riscv_vsub(vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint8mf2_t test___riscv_vsub(vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint8m1_t test___riscv_vsub(vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint8m2_t test___riscv_vsub(vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint8m4_t test___riscv_vsub(vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint8m8_t test___riscv_vsub(vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint16mf4_t test___riscv_vsub(vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint16mf2_t test___riscv_vsub(vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint16m1_t test___riscv_vsub(vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint16m2_t test___riscv_vsub(vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint16m4_t test___riscv_vsub(vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint16m8_t test___riscv_vsub(vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint32mf2_t test___riscv_vsub(vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint32m1_t test___riscv_vsub(vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint32m2_t test___riscv_vsub(vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint32m4_t test___riscv_vsub(vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint32m8_t test___riscv_vsub(vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint64m1_t test___riscv_vsub(vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint64m2_t test___riscv_vsub(vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint64m4_t test___riscv_vsub(vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint64m8_t test___riscv_vsub(vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint8mf8_t test___riscv_vsub(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint8mf4_t test___riscv_vsub(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint8mf2_t test___riscv_vsub(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint8m1_t test___riscv_vsub(vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint8m2_t test___riscv_vsub(vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint8m4_t test___riscv_vsub(vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint8m8_t test___riscv_vsub(vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint16mf4_t test___riscv_vsub(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint16mf2_t test___riscv_vsub(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint16m1_t test___riscv_vsub(vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint16m2_t test___riscv_vsub(vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint16m4_t test___riscv_vsub(vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint16m8_t test___riscv_vsub(vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint32mf2_t test___riscv_vsub(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint32m1_t test___riscv_vsub(vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint32m2_t test___riscv_vsub(vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint32m4_t test___riscv_vsub(vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint32m8_t test___riscv_vsub(vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint64m1_t test___riscv_vsub(vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint64m2_t test___riscv_vsub(vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint64m4_t test___riscv_vsub(vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint64m8_t test___riscv_vsub(vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint8mf8_t test___riscv_vsub(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint8mf4_t test___riscv_vsub(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint8mf2_t test___riscv_vsub(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint8m1_t test___riscv_vsub(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint8m2_t test___riscv_vsub(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint8m4_t test___riscv_vsub(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint8m8_t test___riscv_vsub(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint16mf4_t test___riscv_vsub(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint16mf2_t test___riscv_vsub(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint16m1_t test___riscv_vsub(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint16m2_t test___riscv_vsub(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint16m4_t test___riscv_vsub(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint16m8_t test___riscv_vsub(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint32mf2_t test___riscv_vsub(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint32m1_t test___riscv_vsub(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint32m2_t test___riscv_vsub(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint32m4_t test___riscv_vsub(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint32m8_t test___riscv_vsub(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint64m1_t test___riscv_vsub(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint64m2_t test___riscv_vsub(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint64m4_t test___riscv_vsub(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint64m8_t test___riscv_vsub(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vsub(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vsub(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vsub(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint8m1_t test___riscv_vsub(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint8m2_t test___riscv_vsub(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint8m4_t test___riscv_vsub(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint8m8_t test___riscv_vsub(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vsub(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vsub(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint16m1_t test___riscv_vsub(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint16m2_t test___riscv_vsub(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint16m4_t test___riscv_vsub(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint16m8_t test___riscv_vsub(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vsub(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint32m1_t test___riscv_vsub(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint32m2_t test___riscv_vsub(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint32m4_t test___riscv_vsub(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint32m8_t test___riscv_vsub(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint64m1_t test___riscv_vsub(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint64m2_t test___riscv_vsub(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint64m4_t test___riscv_vsub(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint64m8_t test___riscv_vsub(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_mu-1.C new file mode 100644 index 000000000000..8f327fb5c33a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_mu-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsub_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vsub_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vsub_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vsub_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vsub_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vsub_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vsub_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vsub_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vsub_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vsub_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vsub_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vsub_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vsub_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vsub_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vsub_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vsub_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vsub_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vsub_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vsub_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vsub_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vsub_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vsub_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vsub_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vsub_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vsub_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vsub_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vsub_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vsub_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vsub_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vsub_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vsub_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vsub_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vsub_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vsub_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vsub_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vsub_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vsub_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vsub_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vsub_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vsub_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vsub_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vsub_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vsub_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vsub_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_mu-2.C new file mode 100644 index 000000000000..258a87ca9ef2 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_mu-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsub_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vsub_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vsub_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vsub_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vsub_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vsub_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vsub_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vsub_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vsub_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vsub_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vsub_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vsub_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vsub_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vsub_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vsub_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vsub_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vsub_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vsub_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vsub_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vsub_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vsub_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vsub_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vsub_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vsub_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vsub_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vsub_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vsub_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vsub_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vsub_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vsub_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vsub_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vsub_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vsub_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vsub_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vsub_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vsub_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vsub_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vsub_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vsub_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vsub_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vsub_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vsub_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vsub_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vsub_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_mu-3.C new file mode 100644 index 000000000000..181436d9be3a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_mu-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsub_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vsub_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vsub_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vsub_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vsub_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vsub_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vsub_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vsub_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vsub_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vsub_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vsub_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vsub_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vsub_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vsub_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vsub_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vsub_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vsub_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vsub_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vsub_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vsub_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vsub_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vsub_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vsub_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vsub_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vsub_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vsub_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vsub_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vsub_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vsub_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vsub_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vsub_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vsub_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vsub_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vsub_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vsub_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vsub_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vsub_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vsub_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vsub_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vsub_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vsub_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vsub_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vsub_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vsub_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_tu-1.C new file mode 100644 index 000000000000..d6c91808f60b --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_tu-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsub_tu(vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vsub_tu(vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vsub_tu(vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vsub_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vsub_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vsub_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vsub_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vsub_tu(vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vsub_tu(vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vsub_tu(vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vsub_tu(vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vsub_tu(vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vsub_tu(vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vsub_tu(vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vsub_tu(vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vsub_tu(vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vsub_tu(vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vsub_tu(vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vsub_tu(vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vsub_tu(vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vsub_tu(vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vsub_tu(vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vsub_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vsub_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vsub_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vsub_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vsub_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vsub_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vsub_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vsub_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vsub_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vsub_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vsub_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vsub_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vsub_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vsub_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vsub_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vsub_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vsub_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vsub_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vsub_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vsub_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vsub_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vsub_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_tu-2.C new file mode 100644 index 000000000000..deb888e1e21c --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_tu-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsub_tu(vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vsub_tu(vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vsub_tu(vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vsub_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vsub_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vsub_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vsub_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vsub_tu(vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vsub_tu(vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vsub_tu(vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vsub_tu(vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vsub_tu(vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vsub_tu(vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vsub_tu(vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vsub_tu(vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vsub_tu(vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vsub_tu(vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vsub_tu(vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vsub_tu(vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vsub_tu(vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vsub_tu(vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vsub_tu(vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vsub_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vsub_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vsub_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vsub_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vsub_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vsub_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vsub_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vsub_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vsub_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vsub_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vsub_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vsub_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vsub_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vsub_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vsub_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vsub_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vsub_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vsub_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vsub_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vsub_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vsub_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vsub_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_tu-3.C new file mode 100644 index 000000000000..a47f7921ad6f --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_tu-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsub_tu(vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vsub_tu(vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vsub_tu(vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vsub_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vsub_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vsub_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vsub_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vsub_tu(vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vsub_tu(vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vsub_tu(vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vsub_tu(vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vsub_tu(vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vsub_tu(vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vsub_tu(vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vsub_tu(vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vsub_tu(vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vsub_tu(vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vsub_tu(vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vsub_tu(vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vsub_tu(vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vsub_tu(vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vsub_tu(vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vsub_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vsub_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vsub_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vsub_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vsub_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vsub_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vsub_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vsub_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vsub_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vsub_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vsub_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vsub_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vsub_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vsub_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vsub_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vsub_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vsub_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vsub_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vsub_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vsub_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vsub_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vsub_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_tum-1.C new file mode 100644 index 000000000000..a584de6c7d7a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_tum-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsub_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vsub_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vsub_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vsub_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vsub_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vsub_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vsub_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vsub_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vsub_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vsub_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vsub_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vsub_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vsub_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vsub_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vsub_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vsub_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vsub_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vsub_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vsub_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vsub_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vsub_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vsub_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vsub_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vsub_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vsub_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vsub_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vsub_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vsub_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vsub_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vsub_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vsub_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vsub_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vsub_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vsub_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vsub_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vsub_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vsub_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vsub_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vsub_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vsub_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vsub_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vsub_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vsub_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vsub_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_tum-2.C new file mode 100644 index 000000000000..907382fbdb95 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_tum-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsub_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vsub_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vsub_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vsub_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vsub_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vsub_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vsub_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vsub_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vsub_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vsub_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vsub_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vsub_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vsub_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vsub_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vsub_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vsub_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vsub_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vsub_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vsub_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vsub_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vsub_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vsub_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vsub_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vsub_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vsub_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vsub_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vsub_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vsub_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vsub_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vsub_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vsub_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vsub_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vsub_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vsub_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vsub_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vsub_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vsub_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vsub_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vsub_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vsub_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vsub_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vsub_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vsub_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vsub_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_tum-3.C new file mode 100644 index 000000000000..c76efb1bf313 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_tum-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsub_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vsub_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vsub_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vsub_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vsub_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vsub_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vsub_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vsub_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vsub_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vsub_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vsub_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vsub_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vsub_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vsub_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vsub_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vsub_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vsub_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vsub_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vsub_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vsub_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vsub_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vsub_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vsub_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vsub_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vsub_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vsub_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vsub_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vsub_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vsub_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vsub_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vsub_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vsub_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vsub_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vsub_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vsub_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vsub_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vsub_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vsub_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vsub_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vsub_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vsub_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vsub_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vsub_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vsub_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_tumu-1.C new file mode 100644 index 000000000000..445f3e51c2a9 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_tumu-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsub_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vsub_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vsub_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vsub_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vsub_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vsub_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vsub_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vsub_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vsub_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vsub_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vsub_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vsub_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vsub_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vsub_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vsub_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vsub_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vsub_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vsub_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vsub_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vsub_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vsub_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vsub_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vsub_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vsub_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vsub_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vsub_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vsub_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vsub_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vsub_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vsub_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vsub_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vsub_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vsub_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vsub_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vsub_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vsub_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vsub_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vsub_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vsub_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vsub_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vsub_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vsub_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vsub_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vsub_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_tumu-2.C new file mode 100644 index 000000000000..047c533fc2b6 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_tumu-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsub_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vsub_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vsub_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vsub_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vsub_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vsub_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vsub_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vsub_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vsub_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vsub_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vsub_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vsub_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vsub_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vsub_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vsub_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vsub_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vsub_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vsub_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vsub_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vsub_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vsub_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vsub_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vsub_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vsub_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vsub_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vsub_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vsub_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vsub_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vsub_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vsub_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vsub_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vsub_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vsub_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vsub_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vsub_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vsub_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vsub_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vsub_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vsub_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vsub_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vsub_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vsub_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vsub_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vsub_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_tumu-3.C new file mode 100644 index 000000000000..77ef2083242a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_tumu-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsub_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vsub_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vsub_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vsub_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vsub_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vsub_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vsub_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vsub_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vsub_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vsub_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vsub_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vsub_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vsub_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vsub_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vsub_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vsub_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vsub_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vsub_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vsub_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vsub_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vsub_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vsub_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vsub_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vsub_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vsub_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vsub_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vsub_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vsub_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vsub_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vsub_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vsub_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vsub_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vsub_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vsub_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vsub_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vsub_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vsub_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vsub_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vsub_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vsub_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vsub_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vsub_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vsub_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vsub_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */