From: Ranjani Vaidyanathan Date: Wed, 17 Dec 2025 02:40:45 +0000 (+0800) Subject: pinctrl: imx: Support NXP scmi extended mux config X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=781609002a77712cfbc0515feb985053320d8ca2;p=thirdparty%2Fkernel%2Flinux.git pinctrl: imx: Support NXP scmi extended mux config i.MX94 has special muxing options for certain pins. Their mux settings are not in IOMUXC module. i.MX System Manager Firmware includes new vendor defined pinctrl type to SCMI pinctrl driver to handle these pins. The MUX value field in the IOMUX table is extended to 16 bits where the lower 8 bits represent the current IOMUX value and the upper 8 bits represent the new extended mux added in i.MX94. Signed-off-by: Ranjani Vaidyanathan Signed-off-by: Peng Fan Signed-off-by: Linus Walleij --- diff --git a/drivers/pinctrl/freescale/pinctrl-imx-scmi.c b/drivers/pinctrl/freescale/pinctrl-imx-scmi.c index 4e8ab919b334..04728ad807d3 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx-scmi.c +++ b/drivers/pinctrl/freescale/pinctrl-imx-scmi.c @@ -38,11 +38,12 @@ struct scmi_pinctrl_imx { }; /* SCMI pin control types, aligned with SCMI firmware */ -#define IMX_SCMI_NUM_CFG 4 +#define IMX_SCMI_NUM_CFG 5 #define IMX_SCMI_PIN_MUX 192 #define IMX_SCMI_PIN_CONFIG 193 #define IMX_SCMI_PIN_DAISY_ID 194 #define IMX_SCMI_PIN_DAISY_CFG 195 +#define IMX_SCMI_PIN_EXT 196 #define IMX_SCMI_NO_PAD_CTL BIT(31) #define IMX_SCMI_PAD_SION BIT(30) @@ -118,7 +119,14 @@ static int pinctrl_scmi_imx_dt_node_to_map(struct pinctrl_dev *pctldev, pin_id = mux_reg / 4; - cfg[j++] = pinconf_to_config_packed(IMX_SCMI_PIN_MUX, mux_val); + cfg[j++] = pinconf_to_config_packed(IMX_SCMI_PIN_MUX, (mux_val & 0xFF)); + + if (mux_val & 0xFF00) { + int ext_val = (mux_val & 0xFF00) >> 8; + + cfg[j++] = pinconf_to_config_packed(IMX_SCMI_PIN_EXT, ext_val); + } else + ncfg--; if (!conf_reg || (conf_val & IMX_SCMI_NO_PAD_CTL)) ncfg--;