From: Venkatesh Yadav Abbarapu Date: Wed, 30 Apr 2025 05:09:23 +0000 (+0530) Subject: spi: cadence_qspi: Disable the DAC mode in indirect read X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=79a647c6b7d2a52108bbc2cf8dce2eeb6198f025;p=thirdparty%2Fu-boot.git spi: cadence_qspi: Disable the DAC mode in indirect read Hang has been observed on QEMU, as it starts with indac read and fills sram, but after dma is triggered, it tries dac read instead (based on priority) which gets blocked. Disable the DAC mode in indirect DMA read and enable back for writes as DAC mode is used. Signed-off-by: Venkatesh Yadav Abbarapu Tested-by: Padmarao Begari Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/20250430050923.135256-1-venkatesh.abbarapu@amd.com --- diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c index a00642d09d3..e6f4ba49e77 100644 --- a/drivers/spi/cadence_ospi_versal.c +++ b/drivers/spi/cadence_ospi_versal.c @@ -35,6 +35,10 @@ int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv, bytes_to_dma = n_rx - rx_rem; if (bytes_to_dma) { + if (priv->use_dac_mode) + clrbits_le32(priv->regbase + CQSPI_REG_CONFIG, + CQSPI_REG_CONFIG_DIRECT); + cadence_qspi_apb_enable_linear_mode(false); reg = readl(priv->regbase + CQSPI_REG_CONFIG); reg |= CQSPI_REG_CONFIG_ENBL_DMA; @@ -125,6 +129,9 @@ int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv, memcpy(rxbuf, rxbuf + 1, n_rx - 1); } + if (priv->use_dac_mode) + cadence_qspi_apb_dac_mode_enable(priv->regbase); + return 0; }