From: Konrad Dybcio <quic_kdybcio@quicinc.com>
Date: Wed, 18 Sep 2024 22:57:14 +0000 (+0200)
Subject: arm64: dts: qcom: qdu1000: Affirm IDR0.CCTW on apps_smmu
X-Git-Tag: v6.13-rc1~140^2~22^2~101
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=7a52db70c8c5f4e2f6cf404b6cac10beae43f2bd;p=thirdparty%2Fkernel%2Fstable.git

arm64: dts: qcom: qdu1000: Affirm IDR0.CCTW on apps_smmu

On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent
pagetable walk via the IDR0 register. This however is not respected by
the arm-smmu driver unless dma-coherent is set.

Mark the node as dma-coherent to ensure this (and other) implementations
take this coherency into account.

Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
Tested-by: Steev Klimaszewski <steev@kali.org> # Thinkpad X13s (sc8280xp)
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on sdm845-rb3
Link: https://lore.kernel.org/r/20240919-topic-apps_smmu_coherent-v1-1-5b3a8662403d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---

diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
index 642ca8f0236b3..1dd760e977948 100644
--- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi
+++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
@@ -1412,6 +1412,7 @@
 				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
+			dma-coherent;
 		};
 
 		intc: interrupt-controller@17200000 {