From: Biju Das Date: Tue, 31 May 2022 07:16:57 +0000 (+0100) Subject: clk: renesas: rzg2l: Fix reset status function X-Git-Tag: v5.18.18~552 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=7a7fed646e27853cc4b959c1ae892e757bc2f598;p=thirdparty%2Fkernel%2Fstable.git clk: renesas: rzg2l: Fix reset status function [ Upstream commit 02c96ed9e4cd1f47bfcd10296fec6b0b69d6b3c6 ] As per RZ/G2L HW(Rev.1.10) manual, reset monitor register value 0 means reset signal is not applied (deassert state) and 1 means reset signal is applied (assert state). reset_control_status() expects a positive value if the reset line is asserted. But rzg2l_cpg_status function returns zero for asserted state. This patch fixes the issue by adding double inverted logic, so that reset_control_status returns a positive value if the reset line is asserted. Fixes: ef3c613ccd68 ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC") Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220531071657.104121-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Sasha Levin --- diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index 486d0656c58ac..1068058a3865e 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -744,7 +744,7 @@ static int rzg2l_cpg_status(struct reset_controller_dev *rcdev, unsigned int reg = info->resets[id].off; u32 bitmask = BIT(info->resets[id].bit); - return !(readl(priv->base + CLK_MRST_R(reg)) & bitmask); + return !!(readl(priv->base + CLK_MRST_R(reg)) & bitmask); } static const struct reset_control_ops rzg2l_cpg_reset_ops = {