From: Jani Nikula Date: Wed, 13 May 2026 16:13:25 +0000 (+0300) Subject: drm/i915/irq: constify pipe stats parameters X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=7b18938135fa9a95d1ec1d0ecb575be1c37b72b2;p=thirdparty%2Fkernel%2Flinux.git drm/i915/irq: constify pipe stats parameters The pipe stat irq handling doesn't need to modify the pipe stats arrays. Make them const. Reviewed-by: Ville Syrjälä Link: https://patch.msgid.link/3b7ad6be706ed757b53c6c4e06a3410f6f7520e0.1778688699.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index a1dbf20c2e029..c656d59c75712 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -597,7 +597,7 @@ void i9xx_pipestat_irq_ack(struct intel_display *display, } void i915_pipestat_irq_handler(struct intel_display *display, - u32 iir, u32 pipe_stats[I915_MAX_PIPES]) + u32 iir, const u32 pipe_stats[I915_MAX_PIPES]) { bool blc_event = false; enum pipe pipe; @@ -621,7 +621,7 @@ void i915_pipestat_irq_handler(struct intel_display *display, } void i965_pipestat_irq_handler(struct intel_display *display, - u32 iir, u32 pipe_stats[I915_MAX_PIPES]) + u32 iir, const u32 pipe_stats[I915_MAX_PIPES]) { bool blc_event = false; enum pipe pipe; @@ -648,7 +648,7 @@ void i965_pipestat_irq_handler(struct intel_display *display, } void valleyview_pipestat_irq_handler(struct intel_display *display, - u32 pipe_stats[I915_MAX_PIPES]) + const u32 pipe_stats[I915_MAX_PIPES]) { enum pipe pipe; diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h b/drivers/gpu/drm/i915/display/intel_display_irq.h index e2b1674fae06a..d25b9ea4272b4 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.h +++ b/drivers/gpu/drm/i915/display/intel_display_irq.h @@ -78,9 +78,9 @@ void i915_disable_pipestat(struct intel_display *display, enum pipe pipe, u32 st void i9xx_pipestat_irq_ack(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]); -void i915_pipestat_irq_handler(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]); -void i965_pipestat_irq_handler(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]); -void valleyview_pipestat_irq_handler(struct intel_display *display, u32 pipe_stats[I915_MAX_PIPES]); +void i915_pipestat_irq_handler(struct intel_display *display, u32 iir, const u32 pipe_stats[I915_MAX_PIPES]); +void i965_pipestat_irq_handler(struct intel_display *display, u32 iir, const u32 pipe_stats[I915_MAX_PIPES]); +void valleyview_pipestat_irq_handler(struct intel_display *display, const u32 pipe_stats[I915_MAX_PIPES]); void vlv_display_error_irq_ack(struct intel_display *display, u32 *eir, u32 *dpinvgtt); void vlv_display_error_irq_handler(struct intel_display *display, u32 eir, u32 dpinvgtt);