From: Carl Love <cel@us.ibm.com>
Date: Thu, 9 Sep 2021 19:06:00 +0000 (+0000)
Subject: Add support for the mcrxrx instruction.
X-Git-Tag: VALGRIND_3_18_0~58
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=7bd75320a0ba995be90e469fe4f26f4a925875b9;p=thirdparty%2Fvalgrind.git

Add support for the mcrxrx instruction.

The mcrxrx instruction was introduced in ISA 3.0. It was missed when the
ISA 3.0 support was added to Valgrind.

The mcrxr instruction is not supported on ISA 3.0 and beyond. The
instructions both do a move to the condition register however the mcrxrx
moves [OV|OV32|CA|CA32].  Where the mcrxr instruction moves XER[32:35]
(S0, OV, and CA bits) to the CR.
---

diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
index e30e431581..3dab201476 100644
--- a/VEX/priv/guest_ppc_toIR.c
+++ b/VEX/priv/guest_ppc_toIR.c
@@ -11929,6 +11929,35 @@ static Bool dis_proc_ctl ( const VexAbiInfo* vbi, UInt prefix, UInt theInstr )
       break;
    }
       
+   case 0x240: { // mcrxrx (Move to Cond Register from XER)
+      IRTemp  OV   = newTemp(Ity_I32);
+      IRTemp  CA   = newTemp(Ity_I32);
+      IRTemp  OV32 = newTemp(Ity_I32);
+      IRTemp  CA32 = newTemp(Ity_I32);
+      IRTemp  tmp  = newTemp(Ity_I32);
+
+      if (b21to22 != 0 || b11to20 != 0) {
+         vex_printf("dis_proc_ctl(ppc)(mcrxrx,b21to22|b11to20)\n");
+         return False;
+      }
+      DIP("mcrxrx crf%d\n", crfD);
+      /* Move OV, OV32, CA, CA32 to condition register field BF */
+      assign( OV, binop( Iop_Shl32, getXER_OV_32(), mkU8( 3 ) ));
+      assign( CA, binop( Iop_Shl32, getXER_CA_32(), mkU8( 1 ) ));
+      assign( OV32, binop( Iop_Shl32, getXER_OV32_32(), mkU8( 2 ) ));
+      assign( CA32, getXER_CA32_32() );
+
+      /* Put [OV | OV32 | CA | CA32] into the condition code register */
+      assign( tmp,
+              binop( Iop_Or32,
+                     binop( Iop_Or32, mkexpr ( OV ),  mkexpr ( OV32 ) ),
+                     binop( Iop_Or32, mkexpr ( CA ),  mkexpr ( CA32 ) )
+                 ) );
+
+      putGST_field( PPC_GST_CR,  mkexpr( tmp ), crfD );
+      break;
+   }
+
    case 0x013: 
       // b11to20==0:      mfcr (Move from Cond Register, PPC32 p467)
       // b20==1 & b11==0: mfocrf (Move from One CR Field)
@@ -37514,6 +37543,7 @@ DisResult disInstr_PPC_WRK (
       case 0x200: case 0x013: case 0x153: // mcrxr, mfcr,  mfspr
       case 0x173: case 0x090: case 0x1D3: // mftb,  mtcrf, mtspr
       case 0x220:                         // mcrxrt
+      case 0x240:                         // mcrxrx
          if (dis_proc_ctl( abiinfo, prefix, theInstr )) goto decode_success;
          goto decode_failure;