From: Christophe Lyon <christophe.lyon@linaro.org>
Date: Mon, 29 Mar 2021 12:41:08 +0000 (+0000)
Subject: arm: Fix mult autovectorization patterm for iwmmxt (PR target/99786)
X-Git-Tag: basepoints/gcc-12~328
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=7c1d6e89994109e1b6efb5f13890be5586edeb75;p=thirdparty%2Fgcc.git

arm: Fix mult autovectorization patterm for iwmmxt (PR target/99786)

Similarly to other recently-added autovectorization patterns, mult has
been erroneously enabled for iwmmxt. However, V4HI and V2SI modes are
supported, so we make an exception for them.

The new testcase is derived from gcc.dg/ubsan/pr79904.c, with
additional modes added.

I kept dg-do compile because 'assemble' results in error messages from
the assembler, which are not related to this PR:

Error: selected processor does not support `tmcrr wr0,r4,r5' in ARM mode
Error: selected processor does not support `wstrd wr0,[r0]' in ARM mode
Error: selected processor does not support `wldrd wr0,[r0]' in ARM mode
Error: selected processor does not support `wldrd wr2,.L5' in ARM mode
Error: selected processor does not support `wmulul wr0,wr0,wr2' in ARM mode
Error: selected processor does not support `wstrd wr0,[r0]' in ARM mode
Error: selected processor does not support `wldrd wr0,[r0]' in ARM mode
Error: selected processor does not support `wldrd wr2,.L8' in ARM mode
Error: selected processor does not support `wmulwl wr0,wr0,wr2' in ARM mode
Error: selected processor does not support `wstrd wr0,[r0]' in ARM mode

2021-03-29  Christophe Lyon  <christophe.lyon@linaro.org>

	PR target/99786

	gcc/
	* config/arm/vec-common.md (mul<mode>3): Disable on iwMMXT, expect
	for V4HI and V2SI.

	gcc/testsuite/
	* gcc.target/arm/pr99786.c: New test.
---

diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md
index 48ee6593ccac..0b2b3b1c9ce4 100644
--- a/gcc/config/arm/vec-common.md
+++ b/gcc/config/arm/vec-common.md
@@ -103,7 +103,10 @@
   [(set (match_operand:VDQWH 0 "s_register_operand")
 	(mult:VDQWH (match_operand:VDQWH 1 "s_register_operand")
 		    (match_operand:VDQWH 2 "s_register_operand")))]
-  "ARM_HAVE_<MODE>_ARITH"
+  "ARM_HAVE_<MODE>_ARITH
+   && (!TARGET_REALLY_IWMMXT
+       || <MODE>mode == V4HImode
+       || <MODE>mode == V2SImode)"
 )
 
 (define_expand "smin<mode>3"
diff --git a/gcc/testsuite/gcc.target/arm/pr99786.c b/gcc/testsuite/gcc.target/arm/pr99786.c
new file mode 100644
index 000000000000..11d86f09d121
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/pr99786.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mcpu=*" } { "-mcpu=iwmmxt" } } */
+/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mabi=*" } { "-mabi=iwmmxt" } } */
+/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-march=*" } { "-march=iwmmxt" } } */
+/* { dg-skip-if "Test is specific to ARM mode" { arm*-*-* } { "-mthumb" } { "" } } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-require-effective-target arm_iwmmxt_ok } */
+/* { dg-options "-O3 -mcpu=iwmmxt" } */
+
+typedef signed char V __attribute__((vector_size (8))); 
+
+void
+foo (V *a) 
+{ 
+  *a = *a * 3; 
+}
+
+typedef signed short Vshort __attribute__((vector_size (8))); 
+void
+foo_short (Vshort *a) 
+{ 
+  *a = *a * 3; 
+}
+
+typedef signed int Vint __attribute__((vector_size (8))); 
+void
+foo_int (Vint *a) 
+{ 
+  *a = *a * 3; 
+}