From: Michal Simek Date: Mon, 10 Nov 2025 15:24:13 +0000 (+0100) Subject: clk: versal: Enable clock driver for Versal Gen 2 X-Git-Tag: v2026.04-rc1~52^2~10^2~19 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=7c1e03704830d607935487e3b6c710f063dbe9e8;p=thirdparty%2Fu-boot.git clk: versal: Enable clock driver for Versal Gen 2 Versal Gen 2 is using enhancement SMC format but in near future SCMI client should be used. This patch is just bridging this gap till SCMI server is fully tested. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/e83c665408d1453a464dd02cd2a25bb0ed267131.1762788250.git.michal.simek@amd.com --- diff --git a/configs/amd_versal2_virt_defconfig b/configs/amd_versal2_virt_defconfig index caf4aefe898..4f0c4ba5c96 100644 --- a/configs/amd_versal2_virt_defconfig +++ b/configs/amd_versal2_virt_defconfig @@ -75,6 +75,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SIMPLE_PM_BUS=y CONFIG_CLK_CCF=y CONFIG_CLK_SCMI=y +CONFIG_CLK_VERSAL=y CONFIG_DFU_RAM=y CONFIG_ARM_FFA_TRANSPORT=y CONFIG_FPGA_XILINX=y diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index b884a02bdeb..85cc472b4cb 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -224,7 +224,7 @@ config CLK_VERSACLOCK config CLK_VERSAL bool "Enable clock driver support for Versal" - depends on (ARCH_VERSAL || ARCH_VERSAL_NET) + depends on (ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2) depends on ZYNQMP_FIRMWARE help This clock driver adds support for clock realted settings for diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c index 4a498e22f96..78a2410ca21 100644 --- a/drivers/clk/clk_versal.c +++ b/drivers/clk/clk_versal.c @@ -136,6 +136,25 @@ static int versal_pm_query_legacy(struct versal_pm_query_data qdata, return qdata.qid == PM_QID_CLOCK_GET_NAME ? 0 : ret; } +static int versal_pm_query_enhanced(struct versal_pm_query_data qdata, + u32 *ret_payload) +{ + int ret; + + ret = smc_call_handler(PM_QUERY_DATA, qdata.qid, qdata.arg1, qdata.arg2, + qdata.arg3, 0, 0, ret_payload); + + if (qdata.qid == PM_QID_CLOCK_GET_NAME) { + ret_payload[0] = ret_payload[1]; + ret_payload[1] = ret_payload[2]; + ret_payload[2] = ret_payload[3]; + ret_payload[3] = ret_payload[4]; + ret_payload[4] = 0; + } + + return ret; +} + static inline int versal_is_valid_clock(u32 clk_id) { if (clk_id >= clock_max_idx) @@ -794,6 +813,7 @@ static struct clk_ops versal_clk_ops = { static const struct udevice_id versal_clk_ids[] = { { .compatible = "xlnx,versal-clk", .data = (ulong)versal_pm_query_legacy }, + { .compatible = "xlnx,versal2-clk", .data = (ulong)versal_pm_query_enhanced }, { } };