From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date: Thu, 14 Sep 2023 07:54:37 +0000 (+0800)
Subject: RISC-V: Format VSETVL PASS code
X-Git-Tag: basepoints/gcc-15~6161
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=7c4f6ebe54f4da0097acd07f41782ff6cc39e9a4;p=thirdparty%2Fgcc.git

RISC-V: Format VSETVL PASS code

gcc/ChangeLog:

	* config/riscv/riscv-vsetvl.cc (pass_vsetvl::global_eliminate_vsetvl_insn): Format it.
---

diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index f81361c4ccd1..e9e75fe32863 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -4054,7 +4054,8 @@ pass_vsetvl::global_eliminate_vsetvl_insn (const bb_info *bb) const
     }
 
   /* Step1: Reshape the VL/VTYPE status to make sure everything compatible.  */
-  auto_vec<basic_block> pred_cfg_bbs = get_dominated_by (CDI_POST_DOMINATORS, cfg_bb);
+  auto_vec<basic_block> pred_cfg_bbs
+    = get_dominated_by (CDI_POST_DOMINATORS, cfg_bb);
   FOR_EACH_EDGE (e, ei, cfg_bb->preds)
     {
       sbitmap avout = m_vector_manager->vector_avout[e->src->index];