From: David Daney Date: Mon, 25 Aug 2008 18:39:39 +0000 (+0000) Subject: mips.md (immediate_insn): Move up in file, fix comment typo, reformat. X-Git-Tag: releases/gcc-4.4.0~2883 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=7cede6436921a2f1cc7d93abf2fc2cf96796d4c2;p=thirdparty%2Fgcc.git mips.md (immediate_insn): Move up in file, fix comment typo, reformat. 2008-08-25 David Daney * config/mips/mips.md (immediate_insn): Move up in file, fix comment typo, reformat. (fetchop_bit, atomic_hiqi_op memory_barrier, sync_compare_and_swap, compare_and_swap_12, sync_add, sync_, sync__12, sync_old_, sync_old__12, sync_new_, sync_new__12, sync_nand, sync_nand_12, sync_old_nand, sync_old_nand_12, sync_new_nand, sync_new_nand_12, sync_sub, sync_old_add, sync_old_sub, sync_new_add, sync_new_sub, sync_, sync_old_, sync_new_, sync_nand, sync_old_nand, sync_new_nand, sync_lock_test_and_set, sync_lock_test_and_set, test_and_set_12): Moved to sync.md. (sync.md): Include. * config/mips/sync.md: New file. From-SVN: r139568 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0a8e2206d122..be61419dcd73 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,22 @@ +2008-08-25 David Daney + + * config/mips/mips.md (immediate_insn): Move up in file, fix + comment typo, reformat. + (fetchop_bit, atomic_hiqi_op memory_barrier, + sync_compare_and_swap, compare_and_swap_12, sync_add, + sync_, sync__12, sync_old_, + sync_old__12, sync_new_, sync_new__12, + sync_nand, sync_nand_12, sync_old_nand, + sync_old_nand_12, sync_new_nand, sync_new_nand_12, + sync_sub, sync_old_add, sync_old_sub, + sync_new_add, sync_new_sub, sync_, + sync_old_, sync_new_, sync_nand, + sync_old_nand, sync_new_nand, + sync_lock_test_and_set, sync_lock_test_and_set, + test_and_set_12): Moved to sync.md. + (sync.md): Include. + * config/mips/sync.md: New file. + 2008-08-25 Richard Henderson * dwarf2out.c (def_cfa_1): Don't scale by DWARF_CIE_DATA_ALIGNMENT. diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 4204ec1a6c99..f46db8dfc613 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -820,6 +820,12 @@ (plus "addu") (minus "subu")]) +;; expands to the name of the insn that implements +;; a particular code to operate on immediate values. +(define_code_attr immediate_insn [(ior "ori") + (xor "xori") + (and "andi")]) + ;; is the c.cond.fmt condition associated with a particular code. (define_code_attr fcond [(unordered "un") (uneq "ueq") @@ -835,15 +841,6 @@ (unge "ule") (ungt "ult")]) -;; Atomic fetch bitwise operations. -(define_code_iterator fetchop_bit [ior xor and]) - -;; expands to the name of the insn that implements -;; a particular code to operate in immediate values. -(define_code_attr immediate_insn [(ior "ori") (xor "xori") (and "andi")]) - -;; Atomic HI and QI operations -(define_code_iterator atomic_hiqi_op [plus minus ior xor and]) ;; ......................... ;; @@ -4629,502 +4626,6 @@ } [(set_attr "length" "20")]) -;; Atomic memory operations. - -(define_insn "memory_barrier" - [(set (mem:BLK (scratch)) - (unspec:BLK [(const_int 0)] UNSPEC_MEMORY_BARRIER))] - "GENERATE_SYNC" - "%|sync%-") - -(define_insn "sync_compare_and_swap" - [(set (match_operand:GPR 0 "register_operand" "=&d,&d") - (match_operand:GPR 1 "memory_operand" "+R,R")) - (set (match_dup 1) - (unspec_volatile:GPR [(match_operand:GPR 2 "reg_or_0_operand" "dJ,dJ") - (match_operand:GPR 3 "arith_operand" "I,d")] - UNSPEC_COMPARE_AND_SWAP))] - "GENERATE_LL_SC" -{ - if (which_alternative == 0) - return MIPS_COMPARE_AND_SWAP ("", "li"); - else - return MIPS_COMPARE_AND_SWAP ("", "move"); -} - [(set_attr "length" "32")]) - -(define_expand "sync_compare_and_swap" - [(match_operand:SHORT 0 "register_operand") - (match_operand:SHORT 1 "memory_operand") - (match_operand:SHORT 2 "general_operand") - (match_operand:SHORT 3 "general_operand")] - "GENERATE_LL_SC" -{ - union mips_gen_fn_ptrs generator; - generator.fn_6 = gen_compare_and_swap_12; - mips_expand_atomic_qihi (generator, - operands[0], operands[1], operands[2], operands[3]); - DONE; -}) - -;; Helper insn for mips_expand_atomic_qihi. -(define_insn "compare_and_swap_12" - [(set (match_operand:SI 0 "register_operand" "=&d,&d") - (match_operand:SI 1 "memory_operand" "+R,R")) - (set (match_dup 1) - (unspec_volatile:SI [(match_operand:SI 2 "register_operand" "d,d") - (match_operand:SI 3 "register_operand" "d,d") - (match_operand:SI 4 "reg_or_0_operand" "dJ,dJ") - (match_operand:SI 5 "reg_or_0_operand" "d,J")] - UNSPEC_COMPARE_AND_SWAP_12))] - "GENERATE_LL_SC" -{ - if (which_alternative == 0) - return MIPS_COMPARE_AND_SWAP_12 (MIPS_COMPARE_AND_SWAP_12_NONZERO_OP); - else - return MIPS_COMPARE_AND_SWAP_12 (MIPS_COMPARE_AND_SWAP_12_ZERO_OP); -} - [(set_attr "length" "40,36")]) - -(define_insn "sync_add" - [(set (match_operand:GPR 0 "memory_operand" "+R,R") - (unspec_volatile:GPR - [(plus:GPR (match_dup 0) - (match_operand:GPR 1 "arith_operand" "I,d"))] - UNSPEC_SYNC_OLD_OP))] - "GENERATE_LL_SC" -{ - if (which_alternative == 0) - return MIPS_SYNC_OP ("", "addiu"); - else - return MIPS_SYNC_OP ("", "addu"); -} - [(set_attr "length" "28")]) - -(define_expand "sync_" - [(set (match_operand:SHORT 0 "memory_operand") - (unspec_volatile:SHORT - [(atomic_hiqi_op:SHORT (match_dup 0) - (match_operand:SHORT 1 "general_operand"))] - UNSPEC_SYNC_OLD_OP))] - "GENERATE_LL_SC" -{ - union mips_gen_fn_ptrs generator; - generator.fn_4 = gen_sync__12; - mips_expand_atomic_qihi (generator, - NULL, operands[0], operands[1], NULL); - DONE; -}) - -;; Helper insn for sync_ -(define_insn "sync__12" - [(set (match_operand:SI 0 "memory_operand" "+R") - (unspec_volatile:SI - [(match_operand:SI 1 "register_operand" "d") - (match_operand:SI 2 "register_operand" "d") - (atomic_hiqi_op:SI (match_dup 0) - (match_operand:SI 3 "register_operand" "dJ"))] - UNSPEC_SYNC_OLD_OP_12)) - (clobber (match_scratch:SI 4 "=&d"))] - "GENERATE_LL_SC" -{ - return MIPS_SYNC_OP_12 ("", MIPS_SYNC_OP_12_NOT_NOP); -} - [(set_attr "length" "40")]) - -(define_expand "sync_old_" - [(parallel [ - (set (match_operand:SHORT 0 "register_operand") - (match_operand:SHORT 1 "memory_operand")) - (set (match_dup 1) - (unspec_volatile:SHORT [(atomic_hiqi_op:SHORT - (match_dup 1) - (match_operand:SHORT 2 "general_operand"))] - UNSPEC_SYNC_OLD_OP))])] - "GENERATE_LL_SC" -{ - union mips_gen_fn_ptrs generator; - generator.fn_5 = gen_sync_old__12; - mips_expand_atomic_qihi (generator, - operands[0], operands[1], operands[2], NULL); - DONE; -}) - -;; Helper insn for sync_old_ -(define_insn "sync_old__12" - [(set (match_operand:SI 0 "register_operand" "=&d") - (match_operand:SI 1 "memory_operand" "+R")) - (set (match_dup 1) - (unspec_volatile:SI - [(match_operand:SI 2 "register_operand" "d") - (match_operand:SI 3 "register_operand" "d") - (atomic_hiqi_op:SI (match_dup 0) - (match_operand:SI 4 "register_operand" "dJ"))] - UNSPEC_SYNC_OLD_OP_12)) - (clobber (match_scratch:SI 5 "=&d"))] - "GENERATE_LL_SC" -{ - return MIPS_SYNC_OLD_OP_12 ("", MIPS_SYNC_OLD_OP_12_NOT_NOP, - MIPS_SYNC_OLD_OP_12_NOT_NOP_REG); -} - [(set_attr "length" "40")]) - -(define_expand "sync_new_" - [(parallel [ - (set (match_operand:SHORT 0 "register_operand") - (unspec_volatile:SHORT [(atomic_hiqi_op:SHORT - (match_operand:SHORT 1 "memory_operand") - (match_operand:SHORT 2 "general_operand"))] - UNSPEC_SYNC_NEW_OP)) - (set (match_dup 1) - (unspec_volatile:SHORT [(match_dup 1) (match_dup 2)] - UNSPEC_SYNC_NEW_OP))])] - "GENERATE_LL_SC" -{ - union mips_gen_fn_ptrs generator; - generator.fn_5 = gen_sync_new__12; - mips_expand_atomic_qihi (generator, - operands[0], operands[1], operands[2], NULL); - DONE; -}) - -;; Helper insn for sync_new_ -(define_insn "sync_new__12" - [(set (match_operand:SI 0 "register_operand" "=&d") - (unspec_volatile:SI - [(match_operand:SI 1 "memory_operand" "+R") - (match_operand:SI 2 "register_operand" "d") - (match_operand:SI 3 "register_operand" "d") - (atomic_hiqi_op:SI (match_dup 0) - (match_operand:SI 4 "register_operand" "dJ"))] - UNSPEC_SYNC_NEW_OP_12)) - (set (match_dup 1) - (unspec_volatile:SI - [(match_dup 1) - (match_dup 2) - (match_dup 3) - (match_dup 4)] UNSPEC_SYNC_NEW_OP_12))] - "GENERATE_LL_SC" -{ - return MIPS_SYNC_NEW_OP_12 ("", MIPS_SYNC_NEW_OP_12_NOT_NOP); -} - [(set_attr "length" "40")]) - -(define_expand "sync_nand" - [(set (match_operand:SHORT 0 "memory_operand") - (unspec_volatile:SHORT - [(match_dup 0) - (match_operand:SHORT 1 "general_operand")] - UNSPEC_SYNC_OLD_OP))] - "GENERATE_LL_SC" -{ - union mips_gen_fn_ptrs generator; - generator.fn_4 = gen_sync_nand_12; - mips_expand_atomic_qihi (generator, - NULL, operands[0], operands[1], NULL); - DONE; -}) - -;; Helper insn for sync_nand -(define_insn "sync_nand_12" - [(set (match_operand:SI 0 "memory_operand" "+R") - (unspec_volatile:SI - [(match_operand:SI 1 "register_operand" "d") - (match_operand:SI 2 "register_operand" "d") - (match_dup 0) - (match_operand:SI 3 "register_operand" "dJ")] - UNSPEC_SYNC_OLD_OP_12)) - (clobber (match_scratch:SI 4 "=&d"))] - "GENERATE_LL_SC" -{ - return MIPS_SYNC_OP_12 ("and", MIPS_SYNC_OP_12_NOT_NOT); -} - [(set_attr "length" "44")]) - -(define_expand "sync_old_nand" - [(parallel [ - (set (match_operand:SHORT 0 "register_operand") - (match_operand:SHORT 1 "memory_operand")) - (set (match_dup 1) - (unspec_volatile:SHORT [(match_dup 1) - (match_operand:SHORT 2 "general_operand")] - UNSPEC_SYNC_OLD_OP))])] - "GENERATE_LL_SC" -{ - union mips_gen_fn_ptrs generator; - generator.fn_5 = gen_sync_old_nand_12; - mips_expand_atomic_qihi (generator, - operands[0], operands[1], operands[2], NULL); - DONE; -}) - -;; Helper insn for sync_old_nand -(define_insn "sync_old_nand_12" - [(set (match_operand:SI 0 "register_operand" "=&d") - (match_operand:SI 1 "memory_operand" "+R")) - (set (match_dup 1) - (unspec_volatile:SI - [(match_operand:SI 2 "register_operand" "d") - (match_operand:SI 3 "register_operand" "d") - (match_operand:SI 4 "register_operand" "dJ")] - UNSPEC_SYNC_OLD_OP_12)) - (clobber (match_scratch:SI 5 "=&d"))] - "GENERATE_LL_SC" -{ - return MIPS_SYNC_OLD_OP_12 ("and", MIPS_SYNC_OLD_OP_12_NOT_NOT, - MIPS_SYNC_OLD_OP_12_NOT_NOT_REG); -} - [(set_attr "length" "44")]) - -(define_expand "sync_new_nand" - [(parallel [ - (set (match_operand:SHORT 0 "register_operand") - (unspec_volatile:SHORT [(match_operand:SHORT 1 "memory_operand") - (match_operand:SHORT 2 "general_operand")] - UNSPEC_SYNC_NEW_OP)) - (set (match_dup 1) - (unspec_volatile:SHORT [(match_dup 1) (match_dup 2)] - UNSPEC_SYNC_NEW_OP))])] - "GENERATE_LL_SC" -{ - union mips_gen_fn_ptrs generator; - generator.fn_5 = gen_sync_new_nand_12; - mips_expand_atomic_qihi (generator, - operands[0], operands[1], operands[2], NULL); - DONE; -}) - -;; Helper insn for sync_new_nand -(define_insn "sync_new_nand_12" - [(set (match_operand:SI 0 "register_operand" "=&d") - (unspec_volatile:SI - [(match_operand:SI 1 "memory_operand" "+R") - (match_operand:SI 2 "register_operand" "d") - (match_operand:SI 3 "register_operand" "d") - (match_operand:SI 4 "register_operand" "dJ")] - UNSPEC_SYNC_NEW_OP_12)) - (set (match_dup 1) - (unspec_volatile:SI - [(match_dup 1) - (match_dup 2) - (match_dup 3) - (match_dup 4)] UNSPEC_SYNC_NEW_OP_12))] - "GENERATE_LL_SC" -{ - return MIPS_SYNC_NEW_OP_12 ("and", MIPS_SYNC_NEW_OP_12_NOT_NOT); -} - [(set_attr "length" "40")]) - -(define_insn "sync_sub" - [(set (match_operand:GPR 0 "memory_operand" "+R") - (unspec_volatile:GPR - [(minus:GPR (match_dup 0) - (match_operand:GPR 1 "register_operand" "d"))] - UNSPEC_SYNC_OLD_OP))] - "GENERATE_LL_SC" -{ - return MIPS_SYNC_OP ("", "subu"); -} - [(set_attr "length" "28")]) - -(define_insn "sync_old_add" - [(set (match_operand:GPR 0 "register_operand" "=&d,&d") - (match_operand:GPR 1 "memory_operand" "+R,R")) - (set (match_dup 1) - (unspec_volatile:GPR - [(plus:GPR (match_dup 1) - (match_operand:GPR 2 "arith_operand" "I,d"))] - UNSPEC_SYNC_OLD_OP))] - "GENERATE_LL_SC" -{ - if (which_alternative == 0) - return MIPS_SYNC_OLD_OP ("", "addiu"); - else - return MIPS_SYNC_OLD_OP ("", "addu"); -} - [(set_attr "length" "28")]) - -(define_insn "sync_old_sub" - [(set (match_operand:GPR 0 "register_operand" "=&d") - (match_operand:GPR 1 "memory_operand" "+R")) - (set (match_dup 1) - (unspec_volatile:GPR - [(minus:GPR (match_dup 1) - (match_operand:GPR 2 "register_operand" "d"))] - UNSPEC_SYNC_OLD_OP))] - "GENERATE_LL_SC" -{ - return MIPS_SYNC_OLD_OP ("", "subu"); -} - [(set_attr "length" "28")]) - -(define_insn "sync_new_add" - [(set (match_operand:GPR 0 "register_operand" "=&d,&d") - (plus:GPR (match_operand:GPR 1 "memory_operand" "+R,R") - (match_operand:GPR 2 "arith_operand" "I,d"))) - (set (match_dup 1) - (unspec_volatile:GPR - [(plus:GPR (match_dup 1) (match_dup 2))] - UNSPEC_SYNC_NEW_OP))] - "GENERATE_LL_SC" -{ - if (which_alternative == 0) - return MIPS_SYNC_NEW_OP ("", "addiu"); - else - return MIPS_SYNC_NEW_OP ("", "addu"); -} - [(set_attr "length" "28")]) - -(define_insn "sync_new_sub" - [(set (match_operand:GPR 0 "register_operand" "=&d") - (minus:GPR (match_operand:GPR 1 "memory_operand" "+R") - (match_operand:GPR 2 "register_operand" "d"))) - (set (match_dup 1) - (unspec_volatile:GPR - [(minus:GPR (match_dup 1) (match_dup 2))] - UNSPEC_SYNC_NEW_OP))] - "GENERATE_LL_SC" -{ - return MIPS_SYNC_NEW_OP ("", "subu"); -} - [(set_attr "length" "28")]) - -(define_insn "sync_" - [(set (match_operand:GPR 0 "memory_operand" "+R,R") - (unspec_volatile:GPR - [(fetchop_bit:GPR (match_operand:GPR 1 "uns_arith_operand" "K,d") - (match_dup 0))] - UNSPEC_SYNC_OLD_OP))] - "GENERATE_LL_SC" -{ - if (which_alternative == 0) - return MIPS_SYNC_OP ("", ""); - else - return MIPS_SYNC_OP ("", ""); -} - [(set_attr "length" "28")]) - -(define_insn "sync_old_" - [(set (match_operand:GPR 0 "register_operand" "=&d,&d") - (match_operand:GPR 1 "memory_operand" "+R,R")) - (set (match_dup 1) - (unspec_volatile:GPR - [(fetchop_bit:GPR (match_operand:GPR 2 "uns_arith_operand" "K,d") - (match_dup 1))] - UNSPEC_SYNC_OLD_OP))] - "GENERATE_LL_SC" -{ - if (which_alternative == 0) - return MIPS_SYNC_OLD_OP ("", ""); - else - return MIPS_SYNC_OLD_OP ("", ""); -} - [(set_attr "length" "28")]) - -(define_insn "sync_new_" - [(set (match_operand:GPR 0 "register_operand" "=&d,&d") - (match_operand:GPR 1 "memory_operand" "+R,R")) - (set (match_dup 1) - (unspec_volatile:GPR - [(fetchop_bit:GPR (match_operand:GPR 2 "uns_arith_operand" "K,d") - (match_dup 1))] - UNSPEC_SYNC_NEW_OP))] - "GENERATE_LL_SC" -{ - if (which_alternative == 0) - return MIPS_SYNC_NEW_OP ("", ""); - else - return MIPS_SYNC_NEW_OP ("", ""); -} - [(set_attr "length" "28")]) - -(define_insn "sync_nand" - [(set (match_operand:GPR 0 "memory_operand" "+R,R") - (unspec_volatile:GPR [(match_operand:GPR 1 "uns_arith_operand" "K,d")] - UNSPEC_SYNC_OLD_OP))] - "GENERATE_LL_SC" -{ - if (which_alternative == 0) - return MIPS_SYNC_NAND ("", "andi"); - else - return MIPS_SYNC_NAND ("", "and"); -} - [(set_attr "length" "32")]) - -(define_insn "sync_old_nand" - [(set (match_operand:GPR 0 "register_operand" "=&d,&d") - (match_operand:GPR 1 "memory_operand" "+R,R")) - (set (match_dup 1) - (unspec_volatile:GPR [(match_operand:GPR 2 "uns_arith_operand" "K,d")] - UNSPEC_SYNC_OLD_OP))] - "GENERATE_LL_SC" -{ - if (which_alternative == 0) - return MIPS_SYNC_OLD_NAND ("", "andi"); - else - return MIPS_SYNC_OLD_NAND ("", "and"); -} - [(set_attr "length" "32")]) - -(define_insn "sync_new_nand" - [(set (match_operand:GPR 0 "register_operand" "=&d,&d") - (match_operand:GPR 1 "memory_operand" "+R,R")) - (set (match_dup 1) - (unspec_volatile:GPR [(match_operand:GPR 2 "uns_arith_operand" "K,d")] - UNSPEC_SYNC_NEW_OP))] - "GENERATE_LL_SC" -{ - if (which_alternative == 0) - return MIPS_SYNC_NEW_NAND ("", "andi"); - else - return MIPS_SYNC_NEW_NAND ("", "and"); -} - [(set_attr "length" "32")]) - -(define_insn "sync_lock_test_and_set" - [(set (match_operand:GPR 0 "register_operand" "=&d,&d") - (match_operand:GPR 1 "memory_operand" "+R,R")) - (set (match_dup 1) - (unspec_volatile:GPR [(match_operand:GPR 2 "arith_operand" "I,d")] - UNSPEC_SYNC_EXCHANGE))] - "GENERATE_LL_SC" -{ - if (which_alternative == 0) - return MIPS_SYNC_EXCHANGE ("", "li"); - else - return MIPS_SYNC_EXCHANGE ("", "move"); -} - [(set_attr "length" "24")]) - -(define_expand "sync_lock_test_and_set" - [(match_operand:SHORT 0 "register_operand") - (match_operand:SHORT 1 "memory_operand") - (match_operand:SHORT 2 "general_operand")] - "GENERATE_LL_SC" -{ - union mips_gen_fn_ptrs generator; - generator.fn_5 = gen_test_and_set_12; - mips_expand_atomic_qihi (generator, - operands[0], operands[1], operands[2], NULL); - DONE; -}) - -(define_insn "test_and_set_12" - [(set (match_operand:SI 0 "register_operand" "=&d,&d") - (match_operand:SI 1 "memory_operand" "+R,R")) - (set (match_dup 1) - (unspec_volatile:SI [(match_operand:SI 2 "register_operand" "d,d") - (match_operand:SI 3 "register_operand" "d,d") - (match_operand:SI 4 "arith_operand" "d,J")] - UNSPEC_SYNC_EXCHANGE_12))] - "GENERATE_LL_SC" -{ - if (which_alternative == 0) - return MIPS_SYNC_EXCHANGE_12 (MIPS_SYNC_EXCHANGE_12_NONZERO_OP); - else - return MIPS_SYNC_EXCHANGE_12 (MIPS_SYNC_EXCHANGE_12_ZERO_OP); -} - [(set_attr "length" "28,24")]) ;; Block moves, see mips.c for more details. ;; Argument 0 is the destination @@ -6623,6 +6124,10 @@ (set_attr "can_delay" "no") (set_attr "mode" "")]) +;; Synchronization instructions. + +(include "sync.md") + ; The MIPS Paired-Single Floating Point and MIPS-3D Instructions. (include "mips-ps-3d.md") diff --git a/gcc/config/mips/sync.md b/gcc/config/mips/sync.md new file mode 100644 index 000000000000..0052f46dc9fa --- /dev/null +++ b/gcc/config/mips/sync.md @@ -0,0 +1,523 @@ +;; Machine Description for MIPS based processor synchronization +;; instructions. +;; Copyright (C) 2007, 2008 +;; Free Software Foundation, Inc. + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. + +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +;; Atomic fetch bitwise operations. +(define_code_iterator fetchop_bit [ior xor and]) + +;; Atomic HI and QI operations +(define_code_iterator atomic_hiqi_op [plus minus ior xor and]) + +;; Atomic memory operations. + +(define_insn "memory_barrier" + [(set (mem:BLK (scratch)) + (unspec:BLK [(const_int 0)] UNSPEC_MEMORY_BARRIER))] + "GENERATE_SYNC" + "%|sync%-") + +(define_insn "sync_compare_and_swap" + [(set (match_operand:GPR 0 "register_operand" "=&d,&d") + (match_operand:GPR 1 "memory_operand" "+R,R")) + (set (match_dup 1) + (unspec_volatile:GPR [(match_operand:GPR 2 "reg_or_0_operand" "dJ,dJ") + (match_operand:GPR 3 "arith_operand" "I,d")] + UNSPEC_COMPARE_AND_SWAP))] + "GENERATE_LL_SC" +{ + if (which_alternative == 0) + return MIPS_COMPARE_AND_SWAP ("", "li"); + else + return MIPS_COMPARE_AND_SWAP ("", "move"); +} + [(set_attr "length" "32")]) + +(define_expand "sync_compare_and_swap" + [(match_operand:SHORT 0 "register_operand") + (match_operand:SHORT 1 "memory_operand") + (match_operand:SHORT 2 "general_operand") + (match_operand:SHORT 3 "general_operand")] + "GENERATE_LL_SC" +{ + union mips_gen_fn_ptrs generator; + generator.fn_6 = gen_compare_and_swap_12; + mips_expand_atomic_qihi (generator, + operands[0], operands[1], operands[2], operands[3]); + DONE; +}) + +;; Helper insn for mips_expand_atomic_qihi. +(define_insn "compare_and_swap_12" + [(set (match_operand:SI 0 "register_operand" "=&d,&d") + (match_operand:SI 1 "memory_operand" "+R,R")) + (set (match_dup 1) + (unspec_volatile:SI [(match_operand:SI 2 "register_operand" "d,d") + (match_operand:SI 3 "register_operand" "d,d") + (match_operand:SI 4 "reg_or_0_operand" "dJ,dJ") + (match_operand:SI 5 "reg_or_0_operand" "d,J")] + UNSPEC_COMPARE_AND_SWAP_12))] + "GENERATE_LL_SC" +{ + if (which_alternative == 0) + return MIPS_COMPARE_AND_SWAP_12 (MIPS_COMPARE_AND_SWAP_12_NONZERO_OP); + else + return MIPS_COMPARE_AND_SWAP_12 (MIPS_COMPARE_AND_SWAP_12_ZERO_OP); +} + [(set_attr "length" "40,36")]) + +(define_insn "sync_add" + [(set (match_operand:GPR 0 "memory_operand" "+R,R") + (unspec_volatile:GPR + [(plus:GPR (match_dup 0) + (match_operand:GPR 1 "arith_operand" "I,d"))] + UNSPEC_SYNC_OLD_OP))] + "GENERATE_LL_SC" +{ + if (which_alternative == 0) + return MIPS_SYNC_OP ("", "addiu"); + else + return MIPS_SYNC_OP ("", "addu"); +} + [(set_attr "length" "28")]) + +(define_expand "sync_" + [(set (match_operand:SHORT 0 "memory_operand") + (unspec_volatile:SHORT + [(atomic_hiqi_op:SHORT (match_dup 0) + (match_operand:SHORT 1 "general_operand"))] + UNSPEC_SYNC_OLD_OP))] + "GENERATE_LL_SC" +{ + union mips_gen_fn_ptrs generator; + generator.fn_4 = gen_sync__12; + mips_expand_atomic_qihi (generator, + NULL, operands[0], operands[1], NULL); + DONE; +}) + +;; Helper insn for sync_ +(define_insn "sync__12" + [(set (match_operand:SI 0 "memory_operand" "+R") + (unspec_volatile:SI + [(match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d") + (atomic_hiqi_op:SI (match_dup 0) + (match_operand:SI 3 "register_operand" "dJ"))] + UNSPEC_SYNC_OLD_OP_12)) + (clobber (match_scratch:SI 4 "=&d"))] + "GENERATE_LL_SC" +{ + return MIPS_SYNC_OP_12 ("", MIPS_SYNC_OP_12_NOT_NOP); +} + [(set_attr "length" "40")]) + +(define_expand "sync_old_" + [(parallel [ + (set (match_operand:SHORT 0 "register_operand") + (match_operand:SHORT 1 "memory_operand")) + (set (match_dup 1) + (unspec_volatile:SHORT [(atomic_hiqi_op:SHORT + (match_dup 1) + (match_operand:SHORT 2 "general_operand"))] + UNSPEC_SYNC_OLD_OP))])] + "GENERATE_LL_SC" +{ + union mips_gen_fn_ptrs generator; + generator.fn_5 = gen_sync_old__12; + mips_expand_atomic_qihi (generator, + operands[0], operands[1], operands[2], NULL); + DONE; +}) + +;; Helper insn for sync_old_ +(define_insn "sync_old__12" + [(set (match_operand:SI 0 "register_operand" "=&d") + (match_operand:SI 1 "memory_operand" "+R")) + (set (match_dup 1) + (unspec_volatile:SI + [(match_operand:SI 2 "register_operand" "d") + (match_operand:SI 3 "register_operand" "d") + (atomic_hiqi_op:SI (match_dup 0) + (match_operand:SI 4 "register_operand" "dJ"))] + UNSPEC_SYNC_OLD_OP_12)) + (clobber (match_scratch:SI 5 "=&d"))] + "GENERATE_LL_SC" +{ + return MIPS_SYNC_OLD_OP_12 ("", MIPS_SYNC_OLD_OP_12_NOT_NOP, + MIPS_SYNC_OLD_OP_12_NOT_NOP_REG); +} + [(set_attr "length" "40")]) + +(define_expand "sync_new_" + [(parallel [ + (set (match_operand:SHORT 0 "register_operand") + (unspec_volatile:SHORT [(atomic_hiqi_op:SHORT + (match_operand:SHORT 1 "memory_operand") + (match_operand:SHORT 2 "general_operand"))] + UNSPEC_SYNC_NEW_OP)) + (set (match_dup 1) + (unspec_volatile:SHORT [(match_dup 1) (match_dup 2)] + UNSPEC_SYNC_NEW_OP))])] + "GENERATE_LL_SC" +{ + union mips_gen_fn_ptrs generator; + generator.fn_5 = gen_sync_new__12; + mips_expand_atomic_qihi (generator, + operands[0], operands[1], operands[2], NULL); + DONE; +}) + +;; Helper insn for sync_new_ +(define_insn "sync_new__12" + [(set (match_operand:SI 0 "register_operand" "=&d") + (unspec_volatile:SI + [(match_operand:SI 1 "memory_operand" "+R") + (match_operand:SI 2 "register_operand" "d") + (match_operand:SI 3 "register_operand" "d") + (atomic_hiqi_op:SI (match_dup 0) + (match_operand:SI 4 "register_operand" "dJ"))] + UNSPEC_SYNC_NEW_OP_12)) + (set (match_dup 1) + (unspec_volatile:SI + [(match_dup 1) + (match_dup 2) + (match_dup 3) + (match_dup 4)] UNSPEC_SYNC_NEW_OP_12))] + "GENERATE_LL_SC" +{ + return MIPS_SYNC_NEW_OP_12 ("", MIPS_SYNC_NEW_OP_12_NOT_NOP); +} + [(set_attr "length" "40")]) + +(define_expand "sync_nand" + [(set (match_operand:SHORT 0 "memory_operand") + (unspec_volatile:SHORT + [(match_dup 0) + (match_operand:SHORT 1 "general_operand")] + UNSPEC_SYNC_OLD_OP))] + "GENERATE_LL_SC" +{ + union mips_gen_fn_ptrs generator; + generator.fn_4 = gen_sync_nand_12; + mips_expand_atomic_qihi (generator, + NULL, operands[0], operands[1], NULL); + DONE; +}) + +;; Helper insn for sync_nand +(define_insn "sync_nand_12" + [(set (match_operand:SI 0 "memory_operand" "+R") + (unspec_volatile:SI + [(match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d") + (match_dup 0) + (match_operand:SI 3 "register_operand" "dJ")] + UNSPEC_SYNC_OLD_OP_12)) + (clobber (match_scratch:SI 4 "=&d"))] + "GENERATE_LL_SC" +{ + return MIPS_SYNC_OP_12 ("and", MIPS_SYNC_OP_12_NOT_NOT); +} + [(set_attr "length" "44")]) + +(define_expand "sync_old_nand" + [(parallel [ + (set (match_operand:SHORT 0 "register_operand") + (match_operand:SHORT 1 "memory_operand")) + (set (match_dup 1) + (unspec_volatile:SHORT [(match_dup 1) + (match_operand:SHORT 2 "general_operand")] + UNSPEC_SYNC_OLD_OP))])] + "GENERATE_LL_SC" +{ + union mips_gen_fn_ptrs generator; + generator.fn_5 = gen_sync_old_nand_12; + mips_expand_atomic_qihi (generator, + operands[0], operands[1], operands[2], NULL); + DONE; +}) + +;; Helper insn for sync_old_nand +(define_insn "sync_old_nand_12" + [(set (match_operand:SI 0 "register_operand" "=&d") + (match_operand:SI 1 "memory_operand" "+R")) + (set (match_dup 1) + (unspec_volatile:SI + [(match_operand:SI 2 "register_operand" "d") + (match_operand:SI 3 "register_operand" "d") + (match_operand:SI 4 "register_operand" "dJ")] + UNSPEC_SYNC_OLD_OP_12)) + (clobber (match_scratch:SI 5 "=&d"))] + "GENERATE_LL_SC" +{ + return MIPS_SYNC_OLD_OP_12 ("and", MIPS_SYNC_OLD_OP_12_NOT_NOT, + MIPS_SYNC_OLD_OP_12_NOT_NOT_REG); +} + [(set_attr "length" "44")]) + +(define_expand "sync_new_nand" + [(parallel [ + (set (match_operand:SHORT 0 "register_operand") + (unspec_volatile:SHORT [(match_operand:SHORT 1 "memory_operand") + (match_operand:SHORT 2 "general_operand")] + UNSPEC_SYNC_NEW_OP)) + (set (match_dup 1) + (unspec_volatile:SHORT [(match_dup 1) (match_dup 2)] + UNSPEC_SYNC_NEW_OP))])] + "GENERATE_LL_SC" +{ + union mips_gen_fn_ptrs generator; + generator.fn_5 = gen_sync_new_nand_12; + mips_expand_atomic_qihi (generator, + operands[0], operands[1], operands[2], NULL); + DONE; +}) + +;; Helper insn for sync_new_nand +(define_insn "sync_new_nand_12" + [(set (match_operand:SI 0 "register_operand" "=&d") + (unspec_volatile:SI + [(match_operand:SI 1 "memory_operand" "+R") + (match_operand:SI 2 "register_operand" "d") + (match_operand:SI 3 "register_operand" "d") + (match_operand:SI 4 "register_operand" "dJ")] + UNSPEC_SYNC_NEW_OP_12)) + (set (match_dup 1) + (unspec_volatile:SI + [(match_dup 1) + (match_dup 2) + (match_dup 3) + (match_dup 4)] UNSPEC_SYNC_NEW_OP_12))] + "GENERATE_LL_SC" +{ + return MIPS_SYNC_NEW_OP_12 ("and", MIPS_SYNC_NEW_OP_12_NOT_NOT); +} + [(set_attr "length" "40")]) + +(define_insn "sync_sub" + [(set (match_operand:GPR 0 "memory_operand" "+R") + (unspec_volatile:GPR + [(minus:GPR (match_dup 0) + (match_operand:GPR 1 "register_operand" "d"))] + UNSPEC_SYNC_OLD_OP))] + "GENERATE_LL_SC" +{ + return MIPS_SYNC_OP ("", "subu"); +} + [(set_attr "length" "28")]) + +(define_insn "sync_old_add" + [(set (match_operand:GPR 0 "register_operand" "=&d,&d") + (match_operand:GPR 1 "memory_operand" "+R,R")) + (set (match_dup 1) + (unspec_volatile:GPR + [(plus:GPR (match_dup 1) + (match_operand:GPR 2 "arith_operand" "I,d"))] + UNSPEC_SYNC_OLD_OP))] + "GENERATE_LL_SC" +{ + if (which_alternative == 0) + return MIPS_SYNC_OLD_OP ("", "addiu"); + else + return MIPS_SYNC_OLD_OP ("", "addu"); +} + [(set_attr "length" "28")]) + +(define_insn "sync_old_sub" + [(set (match_operand:GPR 0 "register_operand" "=&d") + (match_operand:GPR 1 "memory_operand" "+R")) + (set (match_dup 1) + (unspec_volatile:GPR + [(minus:GPR (match_dup 1) + (match_operand:GPR 2 "register_operand" "d"))] + UNSPEC_SYNC_OLD_OP))] + "GENERATE_LL_SC" +{ + return MIPS_SYNC_OLD_OP ("", "subu"); +} + [(set_attr "length" "28")]) + +(define_insn "sync_new_add" + [(set (match_operand:GPR 0 "register_operand" "=&d,&d") + (plus:GPR (match_operand:GPR 1 "memory_operand" "+R,R") + (match_operand:GPR 2 "arith_operand" "I,d"))) + (set (match_dup 1) + (unspec_volatile:GPR + [(plus:GPR (match_dup 1) (match_dup 2))] + UNSPEC_SYNC_NEW_OP))] + "GENERATE_LL_SC" +{ + if (which_alternative == 0) + return MIPS_SYNC_NEW_OP ("", "addiu"); + else + return MIPS_SYNC_NEW_OP ("", "addu"); +} + [(set_attr "length" "28")]) + +(define_insn "sync_new_sub" + [(set (match_operand:GPR 0 "register_operand" "=&d") + (minus:GPR (match_operand:GPR 1 "memory_operand" "+R") + (match_operand:GPR 2 "register_operand" "d"))) + (set (match_dup 1) + (unspec_volatile:GPR + [(minus:GPR (match_dup 1) (match_dup 2))] + UNSPEC_SYNC_NEW_OP))] + "GENERATE_LL_SC" +{ + return MIPS_SYNC_NEW_OP ("", "subu"); +} + [(set_attr "length" "28")]) + +(define_insn "sync_" + [(set (match_operand:GPR 0 "memory_operand" "+R,R") + (unspec_volatile:GPR + [(fetchop_bit:GPR (match_operand:GPR 1 "uns_arith_operand" "K,d") + (match_dup 0))] + UNSPEC_SYNC_OLD_OP))] + "GENERATE_LL_SC" +{ + if (which_alternative == 0) + return MIPS_SYNC_OP ("", ""); + else + return MIPS_SYNC_OP ("", ""); +} + [(set_attr "length" "28")]) + +(define_insn "sync_old_" + [(set (match_operand:GPR 0 "register_operand" "=&d,&d") + (match_operand:GPR 1 "memory_operand" "+R,R")) + (set (match_dup 1) + (unspec_volatile:GPR + [(fetchop_bit:GPR (match_operand:GPR 2 "uns_arith_operand" "K,d") + (match_dup 1))] + UNSPEC_SYNC_OLD_OP))] + "GENERATE_LL_SC" +{ + if (which_alternative == 0) + return MIPS_SYNC_OLD_OP ("", ""); + else + return MIPS_SYNC_OLD_OP ("", ""); +} + [(set_attr "length" "28")]) + +(define_insn "sync_new_" + [(set (match_operand:GPR 0 "register_operand" "=&d,&d") + (match_operand:GPR 1 "memory_operand" "+R,R")) + (set (match_dup 1) + (unspec_volatile:GPR + [(fetchop_bit:GPR (match_operand:GPR 2 "uns_arith_operand" "K,d") + (match_dup 1))] + UNSPEC_SYNC_NEW_OP))] + "GENERATE_LL_SC" +{ + if (which_alternative == 0) + return MIPS_SYNC_NEW_OP ("", ""); + else + return MIPS_SYNC_NEW_OP ("", ""); +} + [(set_attr "length" "28")]) + +(define_insn "sync_nand" + [(set (match_operand:GPR 0 "memory_operand" "+R,R") + (unspec_volatile:GPR [(match_operand:GPR 1 "uns_arith_operand" "K,d")] + UNSPEC_SYNC_OLD_OP))] + "GENERATE_LL_SC" +{ + if (which_alternative == 0) + return MIPS_SYNC_NAND ("", "andi"); + else + return MIPS_SYNC_NAND ("", "and"); +} + [(set_attr "length" "32")]) + +(define_insn "sync_old_nand" + [(set (match_operand:GPR 0 "register_operand" "=&d,&d") + (match_operand:GPR 1 "memory_operand" "+R,R")) + (set (match_dup 1) + (unspec_volatile:GPR [(match_operand:GPR 2 "uns_arith_operand" "K,d")] + UNSPEC_SYNC_OLD_OP))] + "GENERATE_LL_SC" +{ + if (which_alternative == 0) + return MIPS_SYNC_OLD_NAND ("", "andi"); + else + return MIPS_SYNC_OLD_NAND ("", "and"); +} + [(set_attr "length" "32")]) + +(define_insn "sync_new_nand" + [(set (match_operand:GPR 0 "register_operand" "=&d,&d") + (match_operand:GPR 1 "memory_operand" "+R,R")) + (set (match_dup 1) + (unspec_volatile:GPR [(match_operand:GPR 2 "uns_arith_operand" "K,d")] + UNSPEC_SYNC_NEW_OP))] + "GENERATE_LL_SC" +{ + if (which_alternative == 0) + return MIPS_SYNC_NEW_NAND ("", "andi"); + else + return MIPS_SYNC_NEW_NAND ("", "and"); +} + [(set_attr "length" "32")]) + +(define_insn "sync_lock_test_and_set" + [(set (match_operand:GPR 0 "register_operand" "=&d,&d") + (match_operand:GPR 1 "memory_operand" "+R,R")) + (set (match_dup 1) + (unspec_volatile:GPR [(match_operand:GPR 2 "arith_operand" "I,d")] + UNSPEC_SYNC_EXCHANGE))] + "GENERATE_LL_SC" +{ + if (which_alternative == 0) + return MIPS_SYNC_EXCHANGE ("", "li"); + else + return MIPS_SYNC_EXCHANGE ("", "move"); +} + [(set_attr "length" "24")]) + +(define_expand "sync_lock_test_and_set" + [(match_operand:SHORT 0 "register_operand") + (match_operand:SHORT 1 "memory_operand") + (match_operand:SHORT 2 "general_operand")] + "GENERATE_LL_SC" +{ + union mips_gen_fn_ptrs generator; + generator.fn_5 = gen_test_and_set_12; + mips_expand_atomic_qihi (generator, + operands[0], operands[1], operands[2], NULL); + DONE; +}) + +(define_insn "test_and_set_12" + [(set (match_operand:SI 0 "register_operand" "=&d,&d") + (match_operand:SI 1 "memory_operand" "+R,R")) + (set (match_dup 1) + (unspec_volatile:SI [(match_operand:SI 2 "register_operand" "d,d") + (match_operand:SI 3 "register_operand" "d,d") + (match_operand:SI 4 "arith_operand" "d,J")] + UNSPEC_SYNC_EXCHANGE_12))] + "GENERATE_LL_SC" +{ + if (which_alternative == 0) + return MIPS_SYNC_EXCHANGE_12 (MIPS_SYNC_EXCHANGE_12_NONZERO_OP); + else + return MIPS_SYNC_EXCHANGE_12 (MIPS_SYNC_EXCHANGE_12_ZERO_OP); +} + [(set_attr "length" "28,24")])