From: Laurent Pinchart Date: Tue, 13 Aug 2024 23:40:10 +0000 (+0300) Subject: arm64: dts: imx8mp: Clarify csis clock frequency X-Git-Tag: v6.12-rc1~188^2~21^2~66 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=7e4030e32a536c47a42bfd7a42b6cb9483ad762c;p=thirdparty%2Flinux.git arm64: dts: imx8mp: Clarify csis clock frequency The DT nodes for the MIPI CSI-2 receivers (MIPI_CSI) configure the CAM1_PIX and CAM2_PIX clocks to 266 MHz through the assigned-clock-rates property, and report that frequency in the clock-frequency property. The i.MX8MP reference manual and datasheet list 266 MHz as a nominal frequency when using both CSI-2 receivers, so all looks normal. In reality, the clock is actually set to 250 MHz, as the selected parent, IMX8MP_SYS_PLL2_1000M, has a 1/4 output that is selected as the closest frequency to 266 MHz. This doesn't break operation of the device, but is clearly misleading. Clarify the clock configuration by selecting the IMX8MP_SYS_PLL2_250M parent, dropping the redundant assigned-clock-rates, and setting clock-frequency to 250 MHz. This doesn't cause any functional change. Signed-off-by: Laurent Pinchart Reviewed-by: Alexander Stein Tested-by: Alexander Stein Signed-off-by: Shawn Guo --- diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 603dfe80216f8..d9b5c40f6460f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1687,7 +1687,7 @@ compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2"; reg = <0x32e40000 0x10000>; interrupts = ; - clock-frequency = <266000000>; + clock-frequency = <250000000>; clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>, @@ -1695,9 +1695,8 @@ clock-names = "pclk", "wrap", "phy", "axi"; assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>, <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_250M>, <&clk IMX8MP_CLK_24M>; - assigned-clock-rates = <266000000>; power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>; status = "disabled"; @@ -1723,7 +1722,7 @@ compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2"; reg = <0x32e50000 0x10000>; interrupts = ; - clock-frequency = <266000000>; + clock-frequency = <250000000>; clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>, <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>, @@ -1731,9 +1730,8 @@ clock-names = "pclk", "wrap", "phy", "axi"; assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>, <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_250M>, <&clk IMX8MP_CLK_24M>; - assigned-clock-rates = <266000000>; power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>; status = "disabled";