From: Dongyan Chen <chendongyan@isrc.iscas.ac.cn>
Date: Mon, 2 Jun 2025 19:30:29 +0000 (-0600)
Subject: [PATCH] RISC-V: Add smcntrpmf extension.
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=7f1ee85470780ffd0542819c53fb7f7f3d05c9a4;p=thirdparty%2Fgcc.git

[PATCH] RISC-V: Add smcntrpmf extension.

This patch support smcntrpmf extension[1].
To enable GCC to recognize and process smcntrpmf extension correctly at compile time.

[1]https://github.com/riscvarchive/riscv-smcntrpmf

gcc/ChangeLog:

	* config/riscv/riscv-ext.def: New extension defs.
	* config/riscv/riscv-ext.opt: Ditto.
	* doc/riscv-ext.texi: Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/arch-59.c: New test.
---

diff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext.def
index dbda8ded397..d0adc2b6569 100644
--- a/gcc/config/riscv/riscv-ext.def
+++ b/gcc/config/riscv/riscv-ext.def
@@ -1675,6 +1675,19 @@ DEFINE_RISCV_EXT(
   /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
   /* EXTRA_EXTENSION_FLAGS */ 0)
 
+DEFINE_RISCV_EXT(
+  /* NAME */ smcntrpmf,
+  /* UPPERCAE_NAME */ SMCNTRPMF,
+  /* FULL_NAME */ "Cycle and instret privilege mode filtering",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({"zicsr"}),
+  /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+  /* FLAG_GROUP */ sm,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+  /* EXTRA_EXTENSION_FLAGS */ 0)
+
 DEFINE_RISCV_EXT(
   /* NAME */ smepmp,
   /* UPPERCAE_NAME */ SMEPMP,
diff --git a/gcc/config/riscv/riscv-ext.opt b/gcc/config/riscv/riscv-ext.opt
index 5e9c5f56ad6..c0dcde65293 100644
--- a/gcc/config/riscv/riscv-ext.opt
+++ b/gcc/config/riscv/riscv-ext.opt
@@ -335,6 +335,8 @@ Mask(SHVSATPA) Var(riscv_sh_subext)
 
 Mask(SMAIA) Var(riscv_sm_subext)
 
+Mask(SMCNTRPMF) Var(riscv_sm_subext)
+
 Mask(SMEPMP) Var(riscv_sm_subext)
 
 Mask(SMMPM) Var(riscv_sm_subext)
diff --git a/gcc/doc/riscv-ext.texi b/gcc/doc/riscv-ext.texi
index 7a22d841d1b..e64c0d653a9 100644
--- a/gcc/doc/riscv-ext.texi
+++ b/gcc/doc/riscv-ext.texi
@@ -494,6 +494,10 @@
 @tab 1.0
 @tab Advanced interrupt architecture extension
 
+@item smcntrpmf
+@tab 1.0
+@tab Cycle and instret privilege mode filtering
+
 @item smepmp
 @tab 1.0
 @tab PMP Enhancements for memory access and execution prevention on Machine mode
diff --git a/gcc/testsuite/gcc.target/riscv/arch-59.c b/gcc/testsuite/gcc.target/riscv/arch-59.c
new file mode 100644
index 00000000000..511cf22106b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-59.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_smcntrpmf -mabi=lp64" } */
+int foo()
+{
+}