From: Julian Seward <jseward@acm.org>
Date: Tue, 26 Sep 2017 15:42:18 +0000 (+0200)
Subject: stage1(): don't assert when presented with an empty instruction vector.
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=7f7d994cabe0bb869e117d5a2e1878072874409d;p=thirdparty%2Fvalgrind.git

stage1(): don't assert when presented with an empty instruction vector.
---

diff --git a/VEX/priv/host_generic_reg_alloc3.c b/VEX/priv/host_generic_reg_alloc3.c
index 7e1e6099d3..528273b9ea 100644
--- a/VEX/priv/host_generic_reg_alloc3.c
+++ b/VEX/priv/host_generic_reg_alloc3.c
@@ -609,8 +609,6 @@ static Bool find_free_rreg(
 static UInt stage1(HInstrVec* instrs_in, UInt ii_total_start, UInt n_rregs,
                    RegAllocChunk** first_chunk, const RegAllocControl* con)
 {
-   vassert(instrs_in->insns_used > 0);
-
    Short ii_vec_start = 0;
 
    RegAllocChunk* chunk  = new_chunk(instrs_in, n_rregs);