From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date: Mon, 11 Sep 2023 03:33:59 +0000 (+0800)
Subject: RISC-V: Use dominance analysis in global vsetvl elimination
X-Git-Tag: basepoints/gcc-15~6304
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=7f9083ffe262cb14c49d042fc6363514badea6cb;p=thirdparty%2Fgcc.git

RISC-V: Use dominance analysis in global vsetvl elimination

I found that it's more reasonable to use existing dominance analysis.

gcc/ChangeLog:

	* config/riscv/riscv-vsetvl.cc (pass_vsetvl::global_eliminate_vsetvl_insn):
	Use dominance analysis.
	(pass_vsetvl::init): Ditto.
	(pass_vsetvl::done): Ditto.
---

diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 134b97737ae5..f81361c4ccd1 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -4054,7 +4054,7 @@ pass_vsetvl::global_eliminate_vsetvl_insn (const bb_info *bb) const
     }
 
   /* Step1: Reshape the VL/VTYPE status to make sure everything compatible.  */
-  hash_set<basic_block> pred_cfg_bbs = get_all_predecessors (cfg_bb);
+  auto_vec<basic_block> pred_cfg_bbs = get_dominated_by (CDI_POST_DOMINATORS, cfg_bb);
   FOR_EACH_EDGE (e, ei, cfg_bb->preds)
     {
       sbitmap avout = m_vector_manager->vector_avout[e->src->index];
@@ -4243,6 +4243,7 @@ pass_vsetvl::init (void)
     {
       /* Initialization of RTL_SSA.  */
       calculate_dominance_info (CDI_DOMINATORS);
+      calculate_dominance_info (CDI_POST_DOMINATORS);
       df_analyze ();
       crtl->ssa = new function_info (cfun);
     }
@@ -4264,6 +4265,7 @@ pass_vsetvl::done (void)
     {
       /* Finalization of RTL_SSA.  */
       free_dominance_info (CDI_DOMINATORS);
+      free_dominance_info (CDI_POST_DOMINATORS);
       if (crtl->ssa->perform_pending_updates ())
 	cleanup_cfg (0);
       delete crtl->ssa;