From: Carl Love <cel@us.ibm.com>
Date: Fri, 11 Jun 2021 15:59:53 +0000 (-0500)
Subject: PPC64 Enable the MMA bit in the HWCAP.
X-Git-Tag: VALGRIND_3_18_0~114
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=7ff2e1c71a97acbfa1c50d1179e1a5863a76f117;p=thirdparty%2Fvalgrind.git

PPC64 Enable the MMA bit in the HWCAP.

The MMA bit should have been enabled when the last of the MMA instructions
were committed.  Also, the header comments about filtering out the DARN
and SCV support should have been updated when DARN and SCV support was added.
---

diff --git a/coregrind/m_initimg/initimg-linux.c b/coregrind/m_initimg/initimg-linux.c
index fc1a32ecf8..73c580333e 100644
--- a/coregrind/m_initimg/initimg-linux.c
+++ b/coregrind/m_initimg/initimg-linux.c
@@ -824,8 +824,9 @@ Addr setup_client_stack( void*  init_sp,
              * explicit support in VEX. Filter out HTM bits since the
              * transaction begin instruction (tbegin) is always failed in
              * Valgrind causing the code to execute the failure path.
-             * Also filter out the DARN random number (bug #411189).
-             * And the SCV syscall (bug #431157).
+             * The DARN random number (bug #411189) and the SCV syscall
+             * (bug #431157) have been fixed.  Can now include them in the
+             * HWCAP bits.
              */
             auxv->u.a_val &= (0x80000000ULL     /* ARCH_2_07 */
                               | 0x20000000ULL   /* DSCR */
@@ -837,7 +838,8 @@ Addr setup_client_stack( void*  init_sp,
                               | 0x00100000ULL   /* PPC_FEATURE2_SCV */
                               | 0x00400000ULL   /* HAS_IEEE128 */
                               | 0x00200000ULL   /* PPC_FEATURE2_DARN */
-                              | 0x00040000ULL); /* ARCH_3_1 */
+                              | 0x00040000ULL   /* ARCH_3_1 */
+                              | 0x00020000ULL); /* MMA instruction support */
          }
 
             break;