From: Richard Genoud Date: Fri, 23 Jan 2026 11:44:40 +0000 (+0100) Subject: mtd: rawnand: sunxi: remove usage of struct sunxi_ccm_reg X-Git-Tag: v2026.04-rc2~24^2~21 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=8034c41d63c985de3bab9980ce81aa70342f64bf;p=thirdparty%2Fu-boot.git mtd: rawnand: sunxi: remove usage of struct sunxi_ccm_reg The sunxi_ccm_reg is legacy, drop its usage from nand related code For that, CCU_NAND0_CLK_CFG and CCU_AHB_GATE1 are added to the clock files when missing. And clock code in sunxi_nand{,_spl}.c and board.c are changed to use the new scheme. Moreover, drop AHB_DIV_1 in favor of the more readable CCM_NAND_CTRL_M/N Suggested-by: Andre Przywara Signed-off-by: Richard Genoud Signed-off-by: Michael Trimarchi --- diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h index 00bdd5f938d..caa4b62b3e2 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h @@ -11,6 +11,7 @@ #define _SUNXI_CLOCK_SUN4I_H #define CCU_AHB_GATE0 0x60 +#define CCU_NAND0_CLK_CFG 0x80 #define CCU_MMC0_CLK_CFG 0x88 #define CCU_MMC1_CLK_CFG 0x8c #define CCU_MMC2_CLK_CFG 0x90 diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index 28c3faccbbc..c8f3a16e7d0 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -11,6 +11,7 @@ #define _SUNXI_CLOCK_SUN6I_H #define CCU_AHB_GATE0 0x060 +#define CCU_NAND0_CLK_CFG 0x080 #define CCU_MMC0_CLK_CFG 0x088 #define CCU_MMC1_CLK_CFG 0x08c #define CCU_MMC2_CLK_CFG 0x090 diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h b/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h index 5ad2163926a..98c69f47f32 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h @@ -14,6 +14,7 @@ #define _SUNXI_CLOCK_SUN8I_A83T_H #define CCU_AHB_GATE0 0x060 +#define CCU_NAND0_CLK_CFG 0x080 #define CCU_MMC0_CLK_CFG 0x088 #define CCU_MMC1_CLK_CFG 0x08c #define CCU_MMC2_CLK_CFG 0x090 diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h index 8d696e533f8..3448f3fb322 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h @@ -12,11 +12,13 @@ #include #endif +#define CCU_NAND0_CLK_CFG 0x400 #define CCU_MMC0_CLK_CFG 0x410 #define CCU_MMC1_CLK_CFG 0x414 #define CCU_MMC2_CLK_CFG 0x418 #define CCU_MMC3_CLK_CFG 0x41c #define CCU_AHB_GATE0 0x580 +#define CCU_AHB_GATE1 0x584 #define CCU_AHB_RESET0_CFG 0x5a0 struct sunxi_ccm_reg { diff --git a/board/sunxi/board.c b/board/sunxi/board.c index e9e3fb9a571..85f20ffe085 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -307,15 +307,16 @@ static void nand_pinmux_setup(void) static void nand_clock_setup(void) { - struct sunxi_ccm_reg *const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + void * const ccm = (void *)SUNXI_CCM_BASE; - setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0)); + setbits_le32(ccm + CCU_AHB_GATE0, + (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0)); #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \ defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I - setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0)); + setbits_le32(ccm + CCU_AHB_RESET0_CFG, (1 << AHB_GATE_OFFSET_NAND0)); #endif - setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1); + setbits_le32(ccm + CCU_NAND0_CLK_CFG, CCM_NAND_CTRL_ENABLE | + CCM_NAND_CTRL_N(0) | CCM_NAND_CTRL_M(1)); } void board_nand_init(void) diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi_nand.c index c6b9b2a4eba..ba2740ed187 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -289,8 +289,7 @@ static inline struct sunxi_nfc *to_sunxi_nfc(struct nand_hw_control *ctrl) static void sunxi_nfc_set_clk_rate(unsigned long hz) { - struct sunxi_ccm_reg *const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + void * const ccm = (void *)SUNXI_CCM_BASE; int div_m, div_n; div_m = (clock_get_pll6() + hz - 1) / hz; @@ -305,14 +304,14 @@ static void sunxi_nfc_set_clk_rate(unsigned long hz) /* config mod clock */ writel(CCM_NAND_CTRL_ENABLE | CCM_NAND_CTRL_PLL6 | CCM_NAND_CTRL_N(div_n) | CCM_NAND_CTRL_M(div_m), - &ccm->nand0_clk_cfg); + ccm + CCU_NAND0_CLK_CFG); /* gate on nand clock */ - setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_NAND0)); + setbits_le32(ccm + CCU_AHB_GATE0, (1 << AHB_GATE_OFFSET_NAND0)); #ifdef CONFIG_MACH_SUN9I - setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA)); + setbits_le32(ccm + CCU_AHB_GATE1, (1 << AHB_GATE_OFFSET_DMA)); #else - setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA)); + setbits_le32(ccm + CCU_AHB_GATE0, (1 << AHB_GATE_OFFSET_DMA)); #endif } diff --git a/drivers/mtd/nand/raw/sunxi_nand_spl.c b/drivers/mtd/nand/raw/sunxi_nand_spl.c index bd6fcd07be5..ab569d8086a 100644 --- a/drivers/mtd/nand/raw/sunxi_nand_spl.c +++ b/drivers/mtd/nand/raw/sunxi_nand_spl.c @@ -531,14 +531,15 @@ unsigned int nand_page_size(void) void nand_deselect(void) { - struct sunxi_ccm_reg *const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + void * const ccm = (void *)SUNXI_CCM_BASE; - clrbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0)); + clrbits_le32(ccm + CCU_AHB_GATE0, + (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0)); #ifdef CONFIG_MACH_SUN9I - clrbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA)); + clrbits_le32(ccm + CCU_AHB_GATE1, (1 << AHB_GATE_OFFSET_DMA)); #else - clrbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA)); + clrbits_le32(ccm + CCU_AHB_GATE0, (1 << AHB_GATE_OFFSET_DMA)); #endif - clrbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1); + clrbits_le32(ccm + CCU_NAND0_CLK_CFG, CCM_NAND_CTRL_ENABLE | + CCM_NAND_CTRL_N(0) | CCM_NAND_CTRL_M(1)); }