From: Christophe Lyon Date: Wed, 10 Jul 2024 22:02:26 +0000 (+0000) Subject: arm: [MVE intrinsics] factorize vcvtbq vcvttq X-Git-Tag: basepoints/gcc-16~5124 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=8035b5b1fdbfe3656013bfdbd3efa2579691ce9f;p=thirdparty%2Fgcc.git arm: [MVE intrinsics] factorize vcvtbq vcvttq Factorize vcvtbq, vcvttq so that they use the same parameterized names. 2024-07-11 Christophe Lyon gcc/ * config/arm/iterators.md (mve_insn): Add VCVTBQ_F16_F32, VCVTTQ_F16_F32, VCVTBQ_F32_F16, VCVTTQ_F32_F16, VCVTBQ_M_F16_F32, VCVTTQ_M_F16_F32, VCVTBQ_M_F32_F16, VCVTTQ_M_F32_F16. (VCVTxQ_F16_F32): New iterator. (VCVTxQ_F32_F16): Likewise. (VCVTxQ_M_F16_F32): Likewise. (VCVTxQ_M_F32_F16): Likewise. * config/arm/mve.md (mve_vcvttq_f32_f16v4sf) (mve_vcvtbq_f32_f16v4sf): Merge into ... (@mve_q_f32_f16v4sf): ... this. (mve_vcvtbq_f16_f32v8hf, mve_vcvttq_f16_f32v8hf): Merge into ... (@mve_q_f16_f32v8hf): ... this. (mve_vcvtbq_m_f16_f32v8hf, mve_vcvttq_m_f16_f32v8hf): Merge into ... (@mve_q_m_f16_f32v8hf): ... this. (mve_vcvtbq_m_f32_f16v4sf, mve_vcvttq_m_f32_f16v4sf): Merge into ... (@mve_q_m_f32_f16v4sf): ... this. --- diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index bf800625fac..b9c39a98ca2 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -964,6 +964,10 @@ (VCMLAQ_M_F "vcmla") (VCMLAQ_ROT90_M_F "vcmla") (VCMLAQ_ROT180_M_F "vcmla") (VCMLAQ_ROT270_M_F "vcmla") (VCMULQ_M_F "vcmul") (VCMULQ_ROT90_M_F "vcmul") (VCMULQ_ROT180_M_F "vcmul") (VCMULQ_ROT270_M_F "vcmul") (VCREATEQ_S "vcreate") (VCREATEQ_U "vcreate") (VCREATEQ_F "vcreate") + (VCVTBQ_F16_F32 "vcvtb") (VCVTTQ_F16_F32 "vcvtt") + (VCVTBQ_F32_F16 "vcvtb") (VCVTTQ_F32_F16 "vcvtt") + (VCVTBQ_M_F16_F32 "vcvtb") (VCVTTQ_M_F16_F32 "vcvtt") + (VCVTBQ_M_F32_F16 "vcvtb") (VCVTTQ_M_F32_F16 "vcvtt") (VCVTQ_FROM_F_S "vcvt") (VCVTQ_FROM_F_U "vcvt") (VCVTQ_M_FROM_F_S "vcvt") (VCVTQ_M_FROM_F_U "vcvt") (VCVTQ_M_N_FROM_F_S "vcvt") (VCVTQ_M_N_FROM_F_U "vcvt") @@ -2948,6 +2952,10 @@ (define_int_iterator VSHLCQ_M [VSHLCQ_M_S VSHLCQ_M_U]) (define_int_iterator VQSHLUQ_M_N [VQSHLUQ_M_N_S]) (define_int_iterator VQSHLUQ_N [VQSHLUQ_N_S]) +(define_int_iterator VCVTxQ_F16_F32 [VCVTBQ_F16_F32 VCVTTQ_F16_F32]) +(define_int_iterator VCVTxQ_F32_F16 [VCVTBQ_F32_F16 VCVTTQ_F32_F16]) +(define_int_iterator VCVTxQ_M_F16_F32 [VCVTBQ_M_F16_F32 VCVTTQ_M_F16_F32]) +(define_int_iterator VCVTxQ_M_F32_F16 [VCVTBQ_M_F32_F16 VCVTTQ_M_F32_F16]) (define_int_iterator DLSTP [DLSTP8 DLSTP16 DLSTP32 DLSTP64]) (define_int_iterator LETP [LETP8 LETP16 LETP32 diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 686620035a8..49a016f5fdd 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -205,33 +205,20 @@ [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_f")) (set_attr "type" "mve_move") ]) -;; -;; [vcvttq_f32_f16]) -;; -(define_insn "mve_vcvttq_f32_f16v4sf" - [ - (set (match_operand:V4SF 0 "s_register_operand" "=w") - (unspec:V4SF [(match_operand:V8HF 1 "s_register_operand" "w")] - VCVTTQ_F32_F16)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vcvtt.f32.f16\t%q0, %q1" - [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvttq_f32_f16v4sf")) - (set_attr "type" "mve_move") -]) ;; -;; [vcvtbq_f32_f16]) +;; [vcvtbq_f32_f16] +;; [vcvttq_f32_f16] ;; -(define_insn "mve_vcvtbq_f32_f16v4sf" +(define_insn "@mve_q_f32_f16v4sf" [ (set (match_operand:V4SF 0 "s_register_operand" "=w") (unspec:V4SF [(match_operand:V8HF 1 "s_register_operand" "w")] - VCVTBQ_F32_F16)) + VCVTxQ_F32_F16)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vcvtb.f32.f16\t%q0, %q1" - [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtbq_f32_f16v4sf")) + ".f32.f16\t%q0, %q1" + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_f32_f16v4sf")) (set_attr "type" "mve_move") ]) @@ -1315,34 +1302,19 @@ ]) ;; -;; [vcvtbq_f16_f32]) -;; -(define_insn "mve_vcvtbq_f16_f32v8hf" - [ - (set (match_operand:V8HF 0 "s_register_operand" "=w") - (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0") - (match_operand:V4SF 2 "s_register_operand" "w")] - VCVTBQ_F16_F32)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vcvtb.f16.f32\t%q0, %q2" - [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtbq_f16_f32v8hf")) - (set_attr "type" "mve_move") -]) - -;; -;; [vcvttq_f16_f32]) +;; [vcvtbq_f16_f32] +;; [vcvttq_f16_f32] ;; -(define_insn "mve_vcvttq_f16_f32v8hf" +(define_insn "@mve_q_f16_f32v8hf" [ (set (match_operand:V8HF 0 "s_register_operand" "=w") (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0") (match_operand:V4SF 2 "s_register_operand" "w")] - VCVTTQ_F16_F32)) + VCVTxQ_F16_F32)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vcvtt.f16.f32\t%q0, %q2" - [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvttq_f16_f32v8hf")) + ".f16.f32\t%q0, %q2" + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_f16_f32v8hf")) (set_attr "type" "mve_move") ]) @@ -2210,73 +2182,41 @@ (set_attr "length""8")]) ;; -;; [vcvtbq_m_f16_f32]) +;; [vcvtbq_m_f16_f32] +;; [vcvttq_m_f16_f32] ;; -(define_insn "mve_vcvtbq_m_f16_f32v8hf" +(define_insn "@mve_q_m_f16_f32v8hf" [ (set (match_operand:V8HF 0 "s_register_operand" "=w") (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0") (match_operand:V4SF 2 "s_register_operand" "w") - (match_operand: 3 "vpr_register_operand" "Up")] - VCVTBQ_M_F16_F32)) + (match_operand:V4BI 3 "vpr_register_operand" "Up")] + VCVTxQ_M_F16_F32)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vcvtbt.f16.f32\t%q0, %q2" - [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtbq_f16_f32v8hf")) + "vpst\;t.f16.f32\t%q0, %q2" + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_f16_f32v8hf")) (set_attr "type" "mve_move") (set_attr "length""8")]) ;; -;; [vcvtbq_m_f32_f16]) +;; [vcvtbq_m_f32_f16] +;; [vcvttq_m_f32_f16] ;; -(define_insn "mve_vcvtbq_m_f32_f16v4sf" +(define_insn "@mve_q_m_f32_f16v4sf" [ (set (match_operand:V4SF 0 "s_register_operand" "=w") (unspec:V4SF [(match_operand:V4SF 1 "s_register_operand" "0") (match_operand:V8HF 2 "s_register_operand" "w") - (match_operand: 3 "vpr_register_operand" "Up")] - VCVTBQ_M_F32_F16)) + (match_operand:V8BI 3 "vpr_register_operand" "Up")] + VCVTxQ_M_F32_F16)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vcvtbt.f32.f16\t%q0, %q2" - [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtbq_f32_f16v4sf")) + "vpst\;t.f32.f16\t%q0, %q2" + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_f32_f16v4sf")) (set_attr "type" "mve_move") (set_attr "length""8")]) -;; -;; [vcvttq_m_f16_f32]) -;; -(define_insn "mve_vcvttq_m_f16_f32v8hf" - [ - (set (match_operand:V8HF 0 "s_register_operand" "=w") - (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0") - (match_operand:V4SF 2 "s_register_operand" "w") - (match_operand: 3 "vpr_register_operand" "Up")] - VCVTTQ_M_F16_F32)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vcvttt.f16.f32\t%q0, %q2" - [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvttq_f16_f32v8hf")) - (set_attr "type" "mve_move") - (set_attr "length""8")]) - -;; -;; [vcvttq_m_f32_f16]) -;; -(define_insn "mve_vcvttq_m_f32_f16v4sf" - [ - (set (match_operand:V4SF 0 "s_register_operand" "=w") - (unspec:V4SF [(match_operand:V4SF 1 "s_register_operand" "0") - (match_operand:V8HF 2 "s_register_operand" "w") - (match_operand: 3 "vpr_register_operand" "Up")] - VCVTTQ_M_F32_F16)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vcvttt.f32.f16\t%q0, %q2" - [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvttq_f32_f16v4sf")) - (set_attr "type" "mve_move") - (set_attr "length""8")]) - ;; ;; [vdupq_m_n_f]) ;;