From: Guodong Xu Date: Thu, 15 Jan 2026 06:51:40 +0000 (+0800) Subject: dt-bindings: riscv: add SpacemiT X100 CPU compatible X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=81a52103b90f5cddc41c34f633c014a956236abc;p=thirdparty%2Fkernel%2Flinux.git dt-bindings: riscv: add SpacemiT X100 CPU compatible Add compatible string for the SpacemiT X100 core. [1] The X100 is a 64-bit RVA23-compliant RISC-V core from SpacemiT. X100 supports the RISC-V vector and hypervisor extensions and all mandatory extersions as required by the RVA23U64 and RVA23S64 profiles, per the definition in 'RVA23 Profile, Version 1.0'. [2] From a microarchieture viewpoint, the X100 features a 4-issue out-of-order pipeline. X100 is used in SpacemiT K3 SoC. Acked-by: Paul Walmsley Acked-by: Krzysztof Kozlowski Link: https://www.spacemit.com/en/spacemit-x100-core/ [1] Link: https://docs.riscv.org/reference/profiles/rva23/_attachments/rva23-profile.pdf [2] Reviewed-by: Yixun Lan Reviewed-by: Heinrich Schuchardt Signed-off-by: Guodong Xu Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-1-6990ac9f4308@riscstar.com Signed-off-by: Yixun Lan --- diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index d733c0bd534fb..5feeb2203050a 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -61,6 +61,7 @@ properties: - sifive,u7 - sifive,u74 - sifive,u74-mc + - spacemit,x100 - spacemit,x60 - thead,c906 - thead,c908