From: John David Anglin <danglin@gcc.gnu.org>
Date: Sun, 15 Feb 2015 15:21:25 +0000 (+0000)
Subject: pa.c (pa_secondary_reload): Request a secondary reload for all floading point loads... 
X-Git-Tag: releases/gcc-4.9.3~353
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=8306569480825241a67cb6d7c12e3dd2b0d3df5b;p=thirdparty%2Fgcc.git

pa.c (pa_secondary_reload): Request a secondary reload for all floading point loads and stores except those...

	* config/pa/pa.c (pa_secondary_reload): Request a secondary reload
	for all floading point loads and stores except those using a register
	index address.
	* config/pa/pa.md: Add new patterns to load a lo_sum DLT operand
	to a register.

From-SVN: r220717
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index e88869b6b25f..1b2bd46fe77f 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2015-02-15  John David Anglin  <danglin@gcc.gnu.org>
+
+	* config/pa/pa.c (pa_secondary_reload): Request a secondary reload
+	for all floading point loads and stores except those using a register
+	index address.
+	* config/pa/pa.md: Add new patterns to load a lo_sum DLT operand
+	to a register.
+
 2015-02-13  John David Anglin  <danglin@gcc.gnu.org>
 
 	* config/pa/constraints.md: Change "Q" and "T" constraints to memory
diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c
index d47de1c261b1..6a17970d1e4a 100644
--- a/gcc/config/pa/pa.c
+++ b/gcc/config/pa/pa.c
@@ -6021,18 +6021,15 @@ pa_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
 	{
 	  x = XEXP (x, 0);
 
-	  /* We don't need an intermediate for indexed and LO_SUM DLT
-	     memory addresses.  When INT14_OK_STRICT is true, it might
-	     appear that we could directly allow register indirect
-	     memory addresses.  However, this doesn't work because we
-	     don't support SUBREGs in floating-point register copies
-	     and reload doesn't tell us when it's going to use a SUBREG.  */
-	  if (IS_INDEX_ADDR_P (x)
-	      || IS_LO_SUM_DLT_ADDR_P (x))
+	  /* We don't need a secondary reload for indexed memory addresses.
+
+	     When INT14_OK_STRICT is true, it might appear that we could
+	     directly allow register indirect memory addresses.  However,
+	     this doesn't work because we don't support SUBREGs in
+	     floating-point register copies and reload doesn't tell us
+	     when it's going to use a SUBREG.  */
+	  if (IS_INDEX_ADDR_P (x))
 	    return NO_REGS;
-
-	  /* Request intermediate general register.  */
-	  return GENERAL_REGS;
 	}
 
       /* Request a secondary reload with a general scratch register
diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index 43b909e35ba5..559b15772c89 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -2680,6 +2680,29 @@
   [(set_attr "type" "binary")
    (set_attr "length" "4")])
 
+(define_insn ""
+ [(set (match_operand:SI 0 "register_operand" "=r")
+       (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
+		  (unspec:SI [(match_operand 2 "" "")] UNSPEC_DLTIND14R)))]
+  "symbolic_operand (operands[2], Pmode)
+   && ! function_label_operand (operands[2], Pmode)
+   && flag_pic"
+  "ldo RT'%G2(%1),%0"
+  [(set_attr "type" "binary")
+   (set_attr "length" "4")])
+
+(define_insn ""
+ [(set (match_operand:DI 0 "register_operand" "=r")
+       (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
+		  (unspec:DI [(match_operand 2 "" "")] UNSPEC_DLTIND14R)))]
+  "symbolic_operand (operands[2], Pmode)
+   && ! function_label_operand (operands[2], Pmode)
+   && TARGET_64BIT
+   && flag_pic"
+  "ldo RT'%G2(%1),%0"
+  [(set_attr "type" "binary")
+   (set_attr "length" "4")])
+
 ;; Always use addil rather than ldil;add sequences.  This allows the
 ;; HP linker to eliminate the dp relocation if the symbolic operand
 ;; lives in the TEXT space.