From: Pan Li Date: Sun, 16 Nov 2025 11:12:35 +0000 (+0800) Subject: RISC-V: Add test for vec_duplicate + vmsne.vv combine case 0 with GR2VR cost 0, 1... X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=83e96a566890d9044a328c71e76b503c2efd1ba0;p=thirdparty%2Fgcc.git RISC-V: Add test for vec_duplicate + vmsne.vv combine case 0 with GR2VR cost 0, 1 and 15 Add asm dump check and run test for vec_duplicate + vmsne.vv combine to vmseq.vx, with the GR2VR cost is 0, 2 and 15. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: Add asm check for vmsne.vx. * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h: Add test helper macros. * gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: Add test data for run test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsne-run-1-i16.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsne-run-1-i32.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsne-run-1-i64.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsne-run-1-i8.c: New test. Signed-off-by: Pan Li --- diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c index 8c8d5c560e9..14a961de054 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c @@ -28,3 +28,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */ /* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmseq.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c index 16490f14c56..738caa81a71 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c @@ -28,3 +28,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */ /* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmseq.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c index b76646dde07..1e7a977cd85 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c @@ -31,3 +31,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */ /* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmseq.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c index f9aba35dcf2..70257d3b547 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c @@ -28,3 +28,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */ /* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmseq.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c index 16881478594..bced1568c3e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c @@ -28,3 +28,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vmadd.vx} } } */ /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ /* { dg-final { scan-assembler-not {vmseq.vx} } } */ +/* { dg-final { scan-assembler-not {vmsne.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c index 042bc1adc8f..cfb52fbadcf 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c @@ -28,3 +28,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vmadd.vx} } } */ /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ /* { dg-final { scan-assembler-not {vmseq.vx} } } */ +/* { dg-final { scan-assembler-not {vmsne.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c index 0f7d23894fb..31846eff9b4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c @@ -28,3 +28,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vmadd.vx} } } */ /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ /* { dg-final { scan-assembler-not {vmseq.vx} } } */ +/* { dg-final { scan-assembler-not {vmsne.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c index 4b1faafc1fb..ea28e2b3dd6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c @@ -28,3 +28,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vmadd.vx} } } */ /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ /* { dg-final { scan-assembler-not {vmseq.vx} } } */ +/* { dg-final { scan-assembler-not {vmsne.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c index 8b4ec62d0ed..e3cddc4fb21 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c @@ -28,3 +28,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vmadd.vx} } } */ /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ /* { dg-final { scan-assembler-not {vmseq.vx} } } */ +/* { dg-final { scan-assembler-not {vmsne.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c index 0a1bd069935..c5cce621f92 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c @@ -28,3 +28,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vmadd.vx} } } */ /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ /* { dg-final { scan-assembler-not {vmseq.vx} } } */ +/* { dg-final { scan-assembler-not {vmsne.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c index 0d0b688edff..6ef8681011e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c @@ -28,3 +28,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vmadd.vx} } } */ /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ /* { dg-final { scan-assembler-not {vmseq.vx} } } */ +/* { dg-final { scan-assembler-not {vmsne.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c index 18d86cb7954..cc789591dc9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c @@ -28,3 +28,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vmadd.vx} } } */ /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ /* { dg-final { scan-assembler-not {vmseq.vx} } } */ +/* { dg-final { scan-assembler-not {vmsne.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h index 950803e31dd..35805a33fcb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h @@ -403,6 +403,7 @@ DEF_AVG_CEIL(int32_t, int64_t) DEF_VX_BINARY_CASE_0_WRAP(T, /, div) \ DEF_VX_BINARY_CASE_0_WRAP(T, %, rem) \ DEF_VX_BINARY_CASE_0_WRAP(T, ==, eq) \ + DEF_VX_BINARY_CASE_0_WRAP(T, !=, ne) \ DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_0_WARP(T), max) \ DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_1_WARP(T), max) \ DEF_VX_BINARY_CASE_2_WRAP(T, MIN_FUNC_0_WARP(T), min) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h index 284992bb132..cb57660e6be 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h @@ -3474,6 +3474,142 @@ int64_t TEST_BINARY_DATA(int64_t, eq)[][3][N] = }, }; +int8_t TEST_BINARY_DATA(int8_t, ne)[][3][N] = +{ + { + { 1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 1, 1, 1, 1, + 1, 1, 1, 1, + }, + }, + { + { 127 }, + { + 0, 0, 0, 0, + 127, 127, 127, 127, + -128, -128, -128, -128, + -2, -2, -2, -2, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 1, 1, 1, 1, + 1, 1, 1, 1, + }, + }, +}; + +int16_t TEST_BINARY_DATA(int16_t, ne)[][3][N] = +{ + { + { 1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 1, 1, 1, 1, + 1, 1, 1, 1, + }, + }, + { + { -32768 }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -32768, -32768, -32768, -32768, + -2, -2, -2, -2, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + 1, 1, 1, 1, + }, + }, +}; + +int32_t TEST_BINARY_DATA(int32_t, ne)[][3][N] = +{ + { + { 1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 1, 1, 1, 1, + 1, 1, 1, 1, + }, + }, + { + { -2147483648 }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -2147483648, -2147483648, -2147483648, -2147483648, + -2, -2, -2, -2, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + 1, 1, 1, 1, + }, + }, +}; + +int64_t TEST_BINARY_DATA(int64_t, ne)[][3][N] = +{ + { + { 1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 1, 1, 1, 1, + 1, 1, 1, 1, + }, + }, + { + { -9223372036854775808ull }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -2, -2, -2, -2, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + 1, 1, 1, 1, + }, + }, +}; + int8_t TEST_BINARY_DATA(int8_t, max)[][3][N] = { { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsne-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsne-run-1-i16.c new file mode 100644 index 00000000000..d42959e8d5b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsne-run-1-i16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int16_t +#define NAME ne + +DEF_VX_BINARY_CASE_0_WRAP(T, !=, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsne-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsne-run-1-i32.c new file mode 100644 index 00000000000..29214cfa33b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsne-run-1-i32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t +#define NAME ne + +DEF_VX_BINARY_CASE_0_WRAP(T, !=, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsne-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsne-run-1-i64.c new file mode 100644 index 00000000000..fbe81136615 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsne-run-1-i64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int64_t +#define NAME ne + +DEF_VX_BINARY_CASE_0_WRAP(T, !=, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsne-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsne-run-1-i8.c new file mode 100644 index 00000000000..58cdf6d5209 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsne-run-1-i8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int8_t +#define NAME ne + +DEF_VX_BINARY_CASE_0_WRAP(T, !=, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h"