From: Julian Seward Date: Wed, 1 Dec 2004 02:24:44 +0000 (+0000) Subject: In the back end, rename the register classes (in enum HRegClass) more X-Git-Tag: svn/VALGRIND_3_0_1^2~731 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=8464fc72e993c7c7be027573c49a0daf8e83c4d8;p=thirdparty%2Fvalgrind.git In the back end, rename the register classes (in enum HRegClass) more consistently, in preparation for SSE instruction selection on x86 host. git-svn-id: svn://svn.valgrind.org/vex/trunk@603 --- diff --git a/VEX/priv/host-generic/h_generic_regs.c b/VEX/priv/host-generic/h_generic_regs.c index adb0be7dd2..94d3274f6b 100644 --- a/VEX/priv/host-generic/h_generic_regs.c +++ b/VEX/priv/host-generic/h_generic_regs.c @@ -43,11 +43,11 @@ void ppHRegClass ( HRegClass hrc ) { switch (hrc) { - case HRcInt: vex_printf("HRcInt32"); break; - case HRcInt64: vex_printf("HRcInt64"); break; - case HRcFloat: vex_printf("HRcFloat"); break; - case HRcVector: vex_printf("HRcVector64"); break; - case HRcVector128: vex_printf("HRcVector128"); break; + case HRcInt32: vex_printf("HRcInt32"); break; + case HRcInt64: vex_printf("HRcInt64"); break; + case HRcFlt64: vex_printf("HRcFlt64"); break; + case HRcVec64: vex_printf("HRcVec64"); break; + case HRcVec128: vex_printf("HRcVec128"); break; default: vpanic("ppHRegClass"); } } @@ -58,11 +58,11 @@ void ppHReg ( HReg r ) Char* maybe_v = hregIsVirtual(r) ? "v" : ""; Int regNo = hregNumber(r); switch (hregClass(r)) { - case HRcInt: vex_printf("%%%sr%d", maybe_v, regNo); return; - case HRcInt64: vex_printf("%%%sR%d", maybe_v, regNo); return; - case HRcFloat: vex_printf("%%%sf%d", maybe_v, regNo); return; - case HRcVector: vex_printf("%%%sv%d", maybe_v, regNo); return; - case HRcVector128: vex_printf("%%%sV%d", maybe_v, regNo); return; + case HRcInt32: vex_printf("%%%sr%d", maybe_v, regNo); return; + case HRcInt64: vex_printf("%%%sR%d", maybe_v, regNo); return; + case HRcFlt64: vex_printf("%%%sF%d", maybe_v, regNo); return; + case HRcVec64: vex_printf("%%%sv%d", maybe_v, regNo); return; + case HRcVec128: vex_printf("%%%sV%d", maybe_v, regNo); return; default: vpanic("ppHReg"); } } diff --git a/VEX/priv/host-generic/h_generic_regs.h b/VEX/priv/host-generic/h_generic_regs.h index 1431b0b730..3ea1b73cf5 100644 --- a/VEX/priv/host-generic/h_generic_regs.h +++ b/VEX/priv/host-generic/h_generic_regs.h @@ -73,13 +73,19 @@ typedef UInt HReg; /* When extending this, do not use any value > 14 or < 0. */ +/* HRegClass describes host register classes which the instruction + selectors can speak about. We would not expect all of them to be + available on any specific host. For example on x86, the available + classes are: Int32, Flt64, Vec128 only. +*/ typedef -enum { HRcINVALID=1, /* NOT A VALID REGISTER CLASS */ - HRcInt=4, /* 32-bit int */ - HRcInt64=5, /* 64-bit int */ - HRcFloat=6, /* 64-bit float */ - HRcVector=7, /* 64-bit SIMD */ - HRcVector128=8 /* 128-bit SIMD */ + enum { + HRcINVALID=1, /* NOT A VALID REGISTER CLASS */ + HRcInt32=4, /* 32-bit int */ + HRcInt64=5, /* 64-bit int */ + HRcFlt64=6, /* 64-bit float */ + HRcVec64=7, /* 64-bit SIMD */ + HRcVec128=8 /* 128-bit SIMD */ } HRegClass; @@ -102,7 +108,7 @@ static inline HReg mkHReg ( UInt regno, HRegClass rc, Bool virtual ) { static inline HRegClass hregClass ( HReg r ) { UInt rc = r; rc = (rc >> 28) & 0x0F; - vassert(rc >= HRcInt || rc <= HRcVector128); + vassert(rc >= HRcInt32 || rc <= HRcVec128); return (HRegClass)rc; } diff --git a/VEX/priv/host-generic/reg_alloc2.c b/VEX/priv/host-generic/reg_alloc2.c index b68a13661f..f251909548 100644 --- a/VEX/priv/host-generic/reg_alloc2.c +++ b/VEX/priv/host-generic/reg_alloc2.c @@ -626,7 +626,7 @@ HInstrArray* doRegisterAllocation ( } /* Need to allocate two 64-bit spill slots for this. */ - if (vreg_info[j].reg_class == HRcVector128) + if (vreg_info[j].reg_class == HRcVec128) vpanic("can't deal with spilling 128-bit values (yet)"); /* Find the lowest-numbered spill slot which is available at the diff --git a/VEX/priv/host-x86/hdefs.c b/VEX/priv/host-x86/hdefs.c index 97dd66cc63..39a44f2b34 100644 --- a/VEX/priv/host-x86/hdefs.c +++ b/VEX/priv/host-x86/hdefs.c @@ -56,38 +56,38 @@ void ppHRegX86 ( HReg reg ) } /* But specific for real regs. */ switch (hregClass(reg)) { - case HRcInt: + case HRcInt32: r = hregNumber(reg); vassert(r >= 0 && r < 8); vex_printf("%s", ireg32_names[r]); return; - case HRcFloat: + case HRcFlt64: r = hregNumber(reg); vassert(r >= 0 && r < 6); vex_printf("%%fake%d", r); return; - case HRcVector: + case HRcVec128: vpanic("ppHRegX86: real vector reg"); default: vpanic("ppHRegX86"); } } -HReg hregX86_EAX ( void ) { return mkHReg(0, HRcInt, False); } -HReg hregX86_ECX ( void ) { return mkHReg(1, HRcInt, False); } -HReg hregX86_EDX ( void ) { return mkHReg(2, HRcInt, False); } -HReg hregX86_EBX ( void ) { return mkHReg(3, HRcInt, False); } -HReg hregX86_ESP ( void ) { return mkHReg(4, HRcInt, False); } -HReg hregX86_EBP ( void ) { return mkHReg(5, HRcInt, False); } -HReg hregX86_ESI ( void ) { return mkHReg(6, HRcInt, False); } -HReg hregX86_EDI ( void ) { return mkHReg(7, HRcInt, False); } +HReg hregX86_EAX ( void ) { return mkHReg(0, HRcInt32, False); } +HReg hregX86_ECX ( void ) { return mkHReg(1, HRcInt32, False); } +HReg hregX86_EDX ( void ) { return mkHReg(2, HRcInt32, False); } +HReg hregX86_EBX ( void ) { return mkHReg(3, HRcInt32, False); } +HReg hregX86_ESP ( void ) { return mkHReg(4, HRcInt32, False); } +HReg hregX86_EBP ( void ) { return mkHReg(5, HRcInt32, False); } +HReg hregX86_ESI ( void ) { return mkHReg(6, HRcInt32, False); } +HReg hregX86_EDI ( void ) { return mkHReg(7, HRcInt32, False); } -HReg hregX86_FAKE0 ( void ) { return mkHReg(0, HRcFloat, False); } -HReg hregX86_FAKE1 ( void ) { return mkHReg(1, HRcFloat, False); } -HReg hregX86_FAKE2 ( void ) { return mkHReg(2, HRcFloat, False); } -HReg hregX86_FAKE3 ( void ) { return mkHReg(3, HRcFloat, False); } -HReg hregX86_FAKE4 ( void ) { return mkHReg(4, HRcFloat, False); } -HReg hregX86_FAKE5 ( void ) { return mkHReg(5, HRcFloat, False); } +HReg hregX86_FAKE0 ( void ) { return mkHReg(0, HRcFlt64, False); } +HReg hregX86_FAKE1 ( void ) { return mkHReg(1, HRcFlt64, False); } +HReg hregX86_FAKE2 ( void ) { return mkHReg(2, HRcFlt64, False); } +HReg hregX86_FAKE3 ( void ) { return mkHReg(3, HRcFlt64, False); } +HReg hregX86_FAKE4 ( void ) { return mkHReg(4, HRcFlt64, False); } +HReg hregX86_FAKE5 ( void ) { return mkHReg(5, HRcFlt64, False); } void getAllocableRegs_X86 ( Int* nregs, HReg** arr ) { @@ -1153,9 +1153,9 @@ X86Instr* genSpill_X86 ( HReg rreg, Int offsetB ) am = X86AMode_IR(offsetB, hregX86_EBP()); switch (hregClass(rreg)) { - case HRcInt: + case HRcInt32: return X86Instr_Alu32M ( Xalu_MOV, X86RI_Reg(rreg), am ); - case HRcFloat: + case HRcFlt64: return X86Instr_FpLdSt ( False/*store*/, 8, rreg, am ); default: ppHRegClass(hregClass(rreg)); @@ -1170,9 +1170,9 @@ X86Instr* genReload_X86 ( HReg rreg, Int offsetB ) vassert(!hregIsVirtual(rreg)); am = X86AMode_IR(offsetB, hregX86_EBP()); switch (hregClass(rreg)) { - case HRcInt: + case HRcInt32: return X86Instr_Alu32R ( Xalu_MOV, X86RMI_Mem(am), rreg ); - case HRcFloat: + case HRcFlt64: return X86Instr_FpLdSt ( True/*load*/, 8, rreg, am ); default: ppHRegClass(hregClass(rreg)); @@ -1186,7 +1186,7 @@ X86Instr* genReload_X86 ( HReg rreg, Int offsetB ) static UInt iregNo ( HReg r ) { UInt n; - vassert(hregClass(r) == HRcInt); + vassert(hregClass(r) == HRcInt32); vassert(!hregIsVirtual(r)); n = hregNumber(r); vassert(n <= 7); @@ -1196,7 +1196,7 @@ static UInt iregNo ( HReg r ) static UInt fregNo ( HReg r ) { UInt n; - vassert(hregClass(r) == HRcFloat); + vassert(hregClass(r) == HRcFlt64); vassert(!hregIsVirtual(r)); n = hregNumber(r); vassert(n <= 5); @@ -1368,7 +1368,7 @@ static UChar* do_fop1_st ( UChar* p, X86FpOp op ) /* Emit f %st(i), 1 <= i <= 5 */ static UChar* do_fop2_st ( UChar* p, X86FpOp op, Int i ) { -# define fake(_n) mkHReg((_n), HRcInt, False) +# define fake(_n) mkHReg((_n), HRcInt32, False) Int subopc; switch (op) { case Xfp_ADD: subopc = 0; break; @@ -1398,7 +1398,7 @@ Int emit_X86Instr ( UChar* buf, Int nbuf, X86Instr* i ) /* Wrap an integer as a int register, for use assembling GrpN insns, in which the greg field is used as a sub-opcode and does not really contain a register. */ -# define fake(_n) mkHReg((_n), HRcInt, False) +# define fake(_n) mkHReg((_n), HRcInt32, False) /* vex_printf("asm ");ppX86Instr(i); vex_printf("\n"); */ diff --git a/VEX/priv/host-x86/isel.c b/VEX/priv/host-x86/isel.c index a912875684..dadf5a5c45 100644 --- a/VEX/priv/host-x86/isel.c +++ b/VEX/priv/host-x86/isel.c @@ -232,14 +232,14 @@ static void addInstr ( ISelEnv* env, X86Instr* instr ) static HReg newVRegI ( ISelEnv* env ) { - HReg reg = mkHReg(env->vreg_ctr, HRcInt, True/*virtual reg*/); + HReg reg = mkHReg(env->vreg_ctr, HRcInt32, True/*virtual reg*/); env->vreg_ctr++; return reg; } static HReg newVRegF ( ISelEnv* env ) { - HReg reg = mkHReg(env->vreg_ctr, HRcFloat, True/*virtual reg*/); + HReg reg = mkHReg(env->vreg_ctr, HRcFlt64, True/*virtual reg*/); env->vreg_ctr++; return reg; } @@ -298,8 +298,8 @@ static Bool isZero32 ( IRExpr* e ) static X86Instr* mk_MOVsd_RR ( HReg src, HReg dst ) { - vassert(hregClass(src) == HRcInt); - vassert(hregClass(dst) == HRcInt); + vassert(hregClass(src) == HRcInt32); + vassert(hregClass(dst) == HRcInt32); return X86Instr_Alu32R(Xalu_MOV, X86RMI_Reg(src), dst); } @@ -639,7 +639,7 @@ static HReg iselIntExpr_R ( ISelEnv* env, IRExpr* e ) # if 0 vex_printf("\n"); ppIRExpr(e); vex_printf("\n"); # endif - vassert(hregClass(r) == HRcInt); + vassert(hregClass(r) == HRcInt32); vassert(hregIsVirtual(r)); return r; } @@ -1181,13 +1181,13 @@ static Bool sane_AMode ( X86AMode* am ) { switch (am->tag) { case Xam_IR: - return hregClass(am->Xam.IR.reg) == HRcInt + return hregClass(am->Xam.IR.reg) == HRcInt32 && (hregIsVirtual(am->Xam.IR.reg) || am->Xam.IR.reg == hregX86_EBP()); case Xam_IRRS: - return hregClass(am->Xam.IRRS.base) == HRcInt + return hregClass(am->Xam.IRRS.base) == HRcInt32 && hregIsVirtual(am->Xam.IRRS.base) - && hregClass(am->Xam.IRRS.index) == HRcInt + && hregClass(am->Xam.IRRS.index) == HRcInt32 && hregIsVirtual(am->Xam.IRRS.index); default: vpanic("sane_AMode: unknown x86 amode tag"); @@ -1253,7 +1253,7 @@ static X86RMI* iselIntExpr_RMI ( ISelEnv* env, IRExpr* e ) case Xrmi_Imm: return rmi; case Xrmi_Reg: - vassert(hregClass(rmi->Xrmi.Reg.reg) == HRcInt); + vassert(hregClass(rmi->Xrmi.Reg.reg) == HRcInt32); vassert(hregIsVirtual(rmi->Xrmi.Reg.reg)); return rmi; case Xrmi_Mem: @@ -1311,7 +1311,7 @@ static X86RI* iselIntExpr_RI ( ISelEnv* env, IRExpr* e ) case Xri_Imm: return ri; case Xrmi_Reg: - vassert(hregClass(ri->Xri.Reg.reg) == HRcInt); + vassert(hregClass(ri->Xri.Reg.reg) == HRcInt32); vassert(hregIsVirtual(ri->Xri.Reg.reg)); return ri; default: @@ -1356,7 +1356,7 @@ static X86RM* iselIntExpr_RM ( ISelEnv* env, IRExpr* e ) /* sanity checks ... */ switch (rm->tag) { case Xrm_Reg: - vassert(hregClass(rm->Xrm.Reg.reg) == HRcInt); + vassert(hregClass(rm->Xrm.Reg.reg) == HRcInt32); vassert(hregIsVirtual(rm->Xrm.Reg.reg)); return rm; case Xrm_Mem: @@ -1573,9 +1573,9 @@ static void iselIntExpr64 ( HReg* rHi, HReg* rLo, ISelEnv* env, IRExpr* e ) # if 0 vex_printf("\n"); ppIRExpr(e); vex_printf("\n"); # endif - vassert(hregClass(*rHi) == HRcInt); + vassert(hregClass(*rHi) == HRcInt32); vassert(hregIsVirtual(*rHi)); - vassert(hregClass(*rLo) == HRcInt); + vassert(hregClass(*rLo) == HRcInt32); vassert(hregIsVirtual(*rLo)); } @@ -2621,11 +2621,11 @@ HInstrArray* iselBB_X86 ( IRBB* bb ) case Ity_I1: case Ity_I8: case Ity_I16: - case Ity_I32: hreg = mkHReg(j++, HRcInt, True); break; - case Ity_I64: hreg = mkHReg(j++, HRcInt, True); - hregHI = mkHReg(j++, HRcInt, True); break; + case Ity_I32: hreg = mkHReg(j++, HRcInt32, True); break; + case Ity_I64: hreg = mkHReg(j++, HRcInt32, True); + hregHI = mkHReg(j++, HRcInt32, True); break; case Ity_F32: - case Ity_F64: hreg = mkHReg(j++, HRcFloat, True); break; + case Ity_F64: hreg = mkHReg(j++, HRcFlt64, True); break; default: ppIRType(bb->tyenv->types[i]); vpanic("iselBB: IRTemp type"); }