From: Christophe JAILLET Date: Sun, 18 Jun 2023 16:24:54 +0000 (+0200) Subject: PCI: Reorder pci_dev fields to reduce holes X-Git-Tag: v6.6-rc1~122^2^2~22 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=849846c41497e481c964b69ab1c65d65958aac28;p=thirdparty%2Fkernel%2Flinux.git PCI: Reorder pci_dev fields to reduce holes Group some bitfield variables to reduce holes. On x86_64, this shrinks the size of 'struct pci_dev' by 16 bytes (from 3576 to 3560) when compiled with 'allmodconfig'. Link: https://lore.kernel.org/r/407b17c3e56764ef2c558898d4ff4c6c04b2d757.1687105455.git.christophe.jaillet@wanadoo.fr Signed-off-by: Christophe JAILLET Signed-off-by: Bjorn Helgaas --- diff --git a/include/linux/pci.h b/include/linux/pci.h index c69a2cc1f4123..1067547572793 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -366,8 +366,8 @@ struct pci_dev { pci_power_t current_state; /* Current operating state. In ACPI, this is D0-D3, D0 being fully functional, and D3 being off. */ - unsigned int imm_ready:1; /* Supports Immediate Readiness */ u8 pm_cap; /* PM capability offset */ + unsigned int imm_ready:1; /* Supports Immediate Readiness */ unsigned int pme_support:5; /* Bitmask of states from which PME# can be generated */ unsigned int pme_poll:1; /* Poll device's PME status bit */ @@ -392,9 +392,9 @@ struct pci_dev { #ifdef CONFIG_PCIEASPM struct pcie_link_state *link_state; /* ASPM link state */ + u16 l1ss; /* L1SS Capability pointer */ unsigned int ltr_path:1; /* Latency Tolerance Reporting supported from root to here */ - u16 l1ss; /* L1SS Capability pointer */ #endif unsigned int pasid_no_tlp:1; /* PASID works without TLP Prefix */ unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */