From: Michal Simek Date: Fri, 15 May 2026 12:47:53 +0000 (+0200) Subject: riscv: Exclude ACLINT for TARGET_XILINX_MBV X-Git-Tag: v2026.10-rc1~4^2~4 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=84b48a918103f0b80719b4f8f42abd9a8ea2582a;p=thirdparty%2Fu-boot.git riscv: Exclude ACLINT for TARGET_XILINX_MBV The Xilinx MicroBlaze V platform does not have an ACLINT (Advanced Core Local Interruptor) hardware block. The timer functionality is provided through a different mechanism. Exclude both RISCV_ACLINT and SPL_RISCV_ACLINT from being implied for TARGET_XILINX_MBV while keeping the default behavior for other generic RISC-V targets that do have ACLINT hardware. spl/u-boot-spl: all -1382 data -360 rodata -200 text -822 Signed-off-by: Michal Simek Reviewed-by: Leo Yu-Chi Liang --- diff --git a/configs/xilinx_mbv32_defconfig b/configs/xilinx_mbv32_defconfig index 9d0111fe8e5..097d6095df2 100644 --- a/configs/xilinx_mbv32_defconfig +++ b/configs/xilinx_mbv32_defconfig @@ -17,6 +17,8 @@ CONFIG_SYS_CLK_FREQ=100000000 CONFIG_BOOT_SCRIPT_OFFSET=0x0 CONFIG_TARGET_XILINX_MBV=y # CONFIG_RISCV_ISA_F is not set +# CONFIG_RISCV_ACLINT is not set +# CONFIG_SPL_RISCV_ACLINT is not set # CONFIG_SPL_SMP is not set # CONFIG_AVAILABLE_HARTS is not set CONFIG_SPL_OPTIMIZE_INLINING=y