From: Julian Seward <jseward@acm.org>
Date: Wed, 20 Jul 2005 00:30:37 +0000 (+0000)
Subject: Add some specialisation rules which are ultimately helpful in reduce
X-Git-Tag: svn/VALGRIND_3_0_1^2~55
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=85478a8425abda931f3e7db4e13d70171195b850;p=thirdparty%2Fvalgrind.git

Add some specialisation rules which are ultimately helpful in reduce
memcheck's false-error rate on inlined strlen and related nasties.



git-svn-id: svn://svn.valgrind.org/vex/trunk@1279
---

diff --git a/VEX/priv/guest-amd64/ghelpers.c b/VEX/priv/guest-amd64/ghelpers.c
index d9226d004d..77022f0ded 100644
--- a/VEX/priv/guest-amd64/ghelpers.c
+++ b/VEX/priv/guest-amd64/ghelpers.c
@@ -913,8 +913,8 @@ IRExpr* guest_amd64_spechelper ( HChar* function_name,
       }
 
       if (isU64(cc_op, AMD64G_CC_OP_SUBL) && isU64(cond, AMD64CondLE)) {
-         /* long sub/cmp, then L (signed less than or equal) 
-            --> test dst <s src */
+         /* long sub/cmp, then LE (signed less than or equal) 
+            --> test dst <=s src */
          return unop(Iop_1Uto64,
                      binop(Iop_CmpLE64S, 
                            binop(Iop_Shl64,cc_dep1,mkU8(32)),
@@ -947,6 +947,16 @@ IRExpr* guest_amd64_spechelper ( HChar* function_name,
                            unop(Iop_64to16,cc_dep2)));
       }
 
+      if (isU64(cc_op, AMD64G_CC_OP_SUBW) && isU64(cond, AMD64CondLE)) {
+         /* 16-bit sub/cmp, then LE (signed less than or equal) 
+            --> test dst <=s src */
+         return unop(Iop_1Uto64,
+                     binop(Iop_CmpLE64S, 
+                           binop(Iop_Shl64,cc_dep1,mkU8(48)),
+                           binop(Iop_Shl64,cc_dep2,mkU8(48))));
+
+      }
+
       /*---------------- SUBB ----------------*/
 
       if (isU64(cc_op, AMD64G_CC_OP_SUBB) && isU64(cond, AMD64CondZ)) {
@@ -1031,6 +1041,17 @@ IRExpr* guest_amd64_spechelper ( HChar* function_name,
 //..                                         mkU32(0)));
 //..       }
 //.. 
+
+      /*---------------- INCB ----------------*/
+
+      if (isU64(cc_op, AMD64G_CC_OP_INCB) && isU64(cond, AMD64CondLE)) {
+         /* 8-bit inc, then LE --> test result <=s 0 */
+         return unop(Iop_1Uto64,
+                     binop(Iop_CmpLE64S, 
+                           binop(Iop_Shl64,cc_dep1,mkU8(56)),
+                           mkU64(0)));
+      }
+
 //..       /*---------------- DECL ----------------*/
 //.. 
 //..       if (isU32(cc_op, AMD64G_CC_OP_DECL) && isU32(cond, X86CondZ)) {