From: Beleswar Padhi Date: Mon, 12 Jan 2026 10:11:02 +0000 (+0530) Subject: ARM: OMAP2+: Pad SPL binary to 8-byte alignment before DTB X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=85f586035d75132b2b60d5e593e1c0049f5d126a;p=thirdparty%2Fu-boot.git ARM: OMAP2+: Pad SPL binary to 8-byte alignment before DTB The OMAP2 SPL linker script (also used for K3 platforms) currently uses a 4-byte alignment directive after the __u_boot_list section. This alignment directive only advances the location counter without padding the actual binary output. When objcopy extracts u-boot-spl-nodtb.bin, it includes only actual data, stopping at the last byte of __u_boot_list (e.g., 0x41c359fc), not an aligned address (e.g., 0x41c35a00). So, when the FIT image containing device trees is concatenated to the SPL binary, it gets appended at this unaligned file size, causing libfdt validation failure. To fix this, move the alignment directive into the __u_boot_list section itself and make it 8-byte aligned as per DT spec. This forces the linker to include padding as part of the section data, ensuring objcopy includes the padding bytes in the binary and the appended FIT image starts at an 8-byte aligned boundary. Reported-by: Anshul Dalal Closes: https://lore.kernel.org/u-boot/DFJ950O0QM0D.380U0N16ZO19E@ti.com Fixes: 0535e46d55d7 ("scripts/dtc: Update to upstream version v1.7.2-35-g52f07dcca47c") Signed-off-by: Beleswar Padhi --- diff --git a/arch/arm/mach-omap2/u-boot-spl.lds b/arch/arm/mach-omap2/u-boot-spl.lds index 3bb759d8a1c..5ad169a37b7 100644 --- a/arch/arm/mach-omap2/u-boot-spl.lds +++ b/arch/arm/mach-omap2/u-boot-spl.lds @@ -35,9 +35,13 @@ SECTIONS . = ALIGN(4); __u_boot_list : { KEEP(*(SORT(__u_boot_list*))); + /* + * Ensure 8-byte alignment at the end of the last section before + * DTB is appended, to satisfy DT spec alignment requirements + */ + . = ALIGN(8); } >.sram - . = ALIGN(4); __image_copy_end = .; _end = .; _image_binary_end = .;