From: Julian Seward Date: Wed, 10 Nov 2004 13:02:48 +0000 (+0000) Subject: Allow tools to tell Vex when it can/can't chase across basic block X-Git-Tag: svn/VALGRIND_3_0_1^2~797 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=8601c98827c8f1e00375dd1cbaa6f0a38e23b3fa;p=thirdparty%2Fvalgrind.git Allow tools to tell Vex when it can/can't chase across basic block boundaries, so as to make the intercept mechanism work properly again. Unfortunately also contains a huge number of tab-to-space whitespace changes in guest-x86/toIR.c. git-svn-id: svn://svn.valgrind.org/vex/trunk@537 --- diff --git a/VEX/head20041019/coregrind/vg_translate.c b/VEX/head20041019/coregrind/vg_translate.c index 1cc0c3fbc6..5530737787 100644 --- a/VEX/head20041019/coregrind/vg_translate.c +++ b/VEX/head20041019/coregrind/vg_translate.c @@ -1629,6 +1629,21 @@ void log_bytes ( Char* bytes, Int nbytes ) 'tid' is the identity of the thread needing this block. */ +/* This stops Vex from chasing into function entry points that we wish + to redirect. Chasing across them obviously defeats the redirect + mechanism, with bad effects for Memcheck, Addrcheck, and possibly + others. */ +static Bool chase_into_ok ( Addr64 addr64 ) +{ + Addr addr = (Addr)addr64; + if (addr != VG_(code_redirect)(addr)) { + if (0) VG_(printf)("not chasing into 0x%x\n", addr); + return False; + } else { + return True; /* ok to chase into 'addr' */ + } +} + Bool VG_(translate) ( ThreadId tid, Addr orig_addr, Bool debugging_translation ) { @@ -1725,7 +1740,9 @@ Bool VG_(translate) ( ThreadId tid, Addr orig_addr, /* Actually do the translation. */ tres = LibVEX_Translate ( InsnSetX86, InsnSetX86, - (Char*)orig_addr, (Addr64)orig_addr, &orig_size, + (Char*)orig_addr, (Addr64)orig_addr, + chase_into_ok, + &orig_size, tmpbuf, N_TMPBUF, &tmpbuf_used, SK_(instrument), VG_(need_to_handle_esp_assignment)() diff --git a/VEX/priv/guest-x86/gdefs.h b/VEX/priv/guest-x86/gdefs.h index 893849628e..beaefe1ccd 100644 --- a/VEX/priv/guest-x86/gdefs.h +++ b/VEX/priv/guest-x86/gdefs.h @@ -24,6 +24,7 @@ IRBB* bbToIR_X86Instr ( UChar* x86code, Addr64 eip, Int* guest_bytes_read, Bool (*byte_accessible)(Addr64), + Bool (*resteerOkFn)(Addr64), Bool host_bigendian ); /* Used by the optimiser to specialise calls to helpers. */ diff --git a/VEX/priv/guest-x86/toIR.c b/VEX/priv/guest-x86/toIR.c index 1bbf41804f..6f7f256f41 100644 --- a/VEX/priv/guest-x86/toIR.c +++ b/VEX/priv/guest-x86/toIR.c @@ -125,10 +125,13 @@ static void stmt ( IRStmt* st ); /* disInstr disassembles an instruction located at &guest_code[delta], and sets *size to its size. If the returned value is Dis_Resteer, - the next guest address is assigned to *whereNext. If chaseJumps - is False, disInstr may not return Dis_Resteer. */ + the next guest address is assigned to *whereNext. disInstr is not + permitted to return Dis_Resteer if either (1) resteerOK is False, + or (2) resteerOkFn, when applied to the address which it wishes to + resteer into, returns False. */ static DisResult disInstr ( /*IN*/ Bool resteerOK, + /*IN*/ Bool (*resteerOkFn) ( Addr64 ), /*IN*/ UInt delta, /*OUT*/ UInt* size, /*OUT*/ Addr64* whereNext ); @@ -143,6 +146,7 @@ IRBB* bbToIR_X86Instr ( UChar* x86code, Addr64 guest_eip_start, Int* guest_bytes_read, Bool (*byte_accessible)(Addr64), + Bool (*chase_into_ok)(Addr64), Bool host_bigendian ) { UInt delta; @@ -182,11 +186,12 @@ IRBB* bbToIR_X86Instr ( UChar* x86code, if (n_instrs > 0) { /* for the first insn, the dispatch loop will have set - %EIP, but for all the others we have to do it ourselves. */ + %EIP, but for all the others we have to do it ourselves. */ stmt( IRStmt_Put( OFFB_EIP, mkU32(guest_eip_bbstart + delta)) ); } - dres = disInstr( resteerOK, delta, &size, &guest_next ); + dres = disInstr( resteerOK, chase_into_ok, + delta, &size, &guest_next ); /* Print the resulting IR, if needed. */ if (vex_traceflags & VEX_TRACE_FE) { @@ -236,12 +241,13 @@ IRBB* bbToIR_X86Instr ( UChar* x86code, case Dis_Resteer: vassert(irbb->next == NULL); /* figure out a new delta to continue at. */ + vassert(chase_into_ok(guest_next)); delta = (UInt)(guest_next - guest_eip_start); n_resteers++; d_resteers++; if (0 && (n_resteers & 0xFF) == 0) - vex_printf("resteer[%d,%d] to %p (delta = %d)\n", - n_resteers, d_resteers, + vex_printf("resteer[%d,%d] to %p (delta = %d)\n", + n_resteers, d_resteers, (void*)(UInt)(guest_next), delta); break; } @@ -470,7 +476,7 @@ static IRExpr* getIReg ( Int sz, UInt archreg ) vassert(sz == 1 || sz == 2 || sz == 4); vassert(archreg < 8); return IRExpr_Get( integerGuestRegOffset(sz,archreg), - szToITy(sz) ); + szToITy(sz) ); } /* Ditto, but write to a reg instead. */ @@ -558,7 +564,7 @@ static IROp mkSizedOp ( IRType ty, IROp op8 ) vassert(op8 == Iop_Add8 || op8 == Iop_Sub8 || op8 == Iop_Mul8 || op8 == Iop_Or8 || op8 == Iop_And8 || op8 == Iop_Xor8 - || op8 == Iop_Shl8 || op8 == Iop_Shr8 || op8 == Iop_Sar8 + || op8 == Iop_Shl8 || op8 == Iop_Shr8 || op8 == Iop_Sar8 || op8 == Iop_CmpEQ8 || op8 == Iop_CmpNE8 || op8 == Iop_Not8 || op8 == Iop_Neg8 ); adj = ty==Ity_I8 ? 0 : (ty==Ity_I16 ? 1 : 2); @@ -892,7 +898,7 @@ static Condcode positiveIse_Condcode ( Condcode cond, appropriately. */ static void helper_ADC ( Int sz, - IRTemp tres, IRTemp ta1, IRTemp ta2 ) + IRTemp tres, IRTemp ta1, IRTemp ta2 ) { UInt thunkOp; IRType ty = szToITy(sz); @@ -907,7 +913,7 @@ static void helper_ADC ( Int sz, /* oldc = old carry flag, 0 or 1 */ assign( oldc, binop(Iop_And32, mk_calculate_eflags_c(), - mkU32(1)) ); + mkU32(1)) ); assign( oldcn, narrowTo(ty, mkexpr(oldc)) ); @@ -926,7 +932,7 @@ static void helper_ADC ( Int sz, appropriately. */ static void helper_SBB ( Int sz, - IRTemp tres, IRTemp ta1, IRTemp ta2 ) + IRTemp tres, IRTemp ta1, IRTemp ta2 ) { UInt thunkOp; IRType ty = szToITy(sz); @@ -941,7 +947,7 @@ static void helper_SBB ( Int sz, /* oldc = old carry flag, 0 or 1 */ assign( oldc, binop(Iop_And32, mk_calculate_eflags_c(), - mkU32(1)) ); + mkU32(1)) ); assign( oldcn, narrowTo(ty, mkexpr(oldc)) ); @@ -964,19 +970,19 @@ static void helper_SBB ( Int sz, //-- //-- #define VG_CPU_VENDOR_GENERIC 0 //-- #define VG_CPU_VENDOR_INTEL 1 -//-- #define VG_CPU_VENDOR_AMD 2 +//-- #define VG_CPU_VENDOR_AMD 2 //-- //-- static Int cpu_vendor = VG_CPU_VENDOR_GENERIC; //-- //-- static const struct cpu_vendor { -//-- const Char *vendorstr; -//-- Int vendorid; +//-- const Char *vendorstr; +//-- Int vendorid; //-- } cpu_vendors[] = { -//-- { "GenuineIntel", VG_CPU_VENDOR_INTEL }, -//-- { "AuthenticAMD", VG_CPU_VENDOR_AMD }, +//-- { "GenuineIntel", VG_CPU_VENDOR_INTEL }, +//-- { "AuthenticAMD", VG_CPU_VENDOR_AMD }, //-- }; //-- -//-- static Int cpuid_level = -2; /* -2 -> not initialized */ +//-- static Int cpuid_level = -2; /* -2 -> not initialized */ //-- static UInt cpu_features[VG_N_FEATURE_WORDS]; //-- //-- /* Standard macro to see if a specific flag is changeable */ @@ -1024,8 +1030,8 @@ static void helper_SBB ( Int sz, //-- //-- for(i = 0; i < sizeof(cpu_vendors)/sizeof(*cpu_vendors); i++) //-- if (VG_(memcmp)(vendorstr, cpu_vendors[i].vendorstr, 12) == 0) { -//-- cpu_vendor = cpu_vendors[i].vendorid; -//-- break; +//-- cpu_vendor = cpu_vendors[i].vendorid; +//-- break; //-- } //-- //-- if (cpuid_level >= 1) @@ -1061,72 +1067,72 @@ static void helper_SBB ( Int sz, //-- extensions which don't have any user-mode visible effect (but the //-- client may find interesting). //-- */ -#define VG_X86_SUPPORTED_FEATURES \ - ((1 << VG_X86_FEAT_FPU) | \ - (1 << VG_X86_FEAT_VME) | \ - (1 << VG_X86_FEAT_DE) | \ - (1 << VG_X86_FEAT_PSE) | \ - (1 << VG_X86_FEAT_TSC) | \ - (0 << VG_X86_FEAT_MSR) | \ - (1 << VG_X86_FEAT_PAE) | \ - (1 << VG_X86_FEAT_MCE) | \ - (1 << VG_X86_FEAT_CX8) | \ - (1 << VG_X86_FEAT_APIC) | \ - (0 << VG_X86_FEAT_SEP) | \ - (1 << VG_X86_FEAT_MTRR) | \ - (1 << VG_X86_FEAT_PGE) | \ - (1 << VG_X86_FEAT_MCA) | \ - (1 << VG_X86_FEAT_CMOV) | \ - (1 << VG_X86_FEAT_PAT) | \ - (1 << VG_X86_FEAT_PSE36) | \ - (0 << VG_X86_FEAT_CLFSH) | \ - (1 << VG_X86_FEAT_DS) | \ - (1 << VG_X86_FEAT_ACPI) | \ - (1 << VG_X86_FEAT_MMX) | \ - (1 << VG_X86_FEAT_FXSR) | \ - (1 << VG_X86_FEAT_SSE) | \ - (1 << VG_X86_FEAT_SSE2) | \ - (1 << VG_X86_FEAT_SS) | \ - (1 << VG_X86_FEAT_HT) | \ - (1 << VG_X86_FEAT_TM) | \ - (0 << VG_X86_FEAT_IA64) | \ - (1 << VG_X86_FEAT_PBE)) - -#define VG_AMD_SUPPORTED_FEATURES \ - ((0 << (VG_AMD_FEAT_SYSCALL % 32)) | \ - (0 << (VG_AMD_FEAT_NXP % 32)) | \ - (1 << (VG_AMD_FEAT_MMXEXT % 32)) | \ - (0 << (VG_AMD_FEAT_FFXSR % 32)) | \ - (0 << (VG_AMD_FEAT_LONGMODE % 32)) | \ - (0 << (VG_AMD_FEAT_3DNOWEXT % 32)) | \ - (0 << (VG_AMD_FEAT_3DNOW % 32)) | \ - /* Common bits between standard features and AMD features */ \ - (1 << VG_X86_FEAT_FPU) | \ - (1 << VG_X86_FEAT_VME) | \ - (1 << VG_X86_FEAT_DE) | \ - (1 << VG_X86_FEAT_PSE) | \ - (1 << VG_X86_FEAT_TSC) | \ - (0 << VG_X86_FEAT_MSR) | \ - (1 << VG_X86_FEAT_PAE) | \ - (1 << VG_X86_FEAT_MCE) | \ - (1 << VG_X86_FEAT_CX8) | \ - (1 << VG_X86_FEAT_APIC) | \ - (1 << VG_X86_FEAT_MTRR) | \ - (1 << VG_X86_FEAT_PGE) | \ - (1 << VG_X86_FEAT_MCA) | \ - (1 << VG_X86_FEAT_CMOV) | \ - (1 << VG_X86_FEAT_PAT) | \ - (1 << VG_X86_FEAT_PSE36) | \ - (1 << VG_X86_FEAT_MMX) | \ - (1 << VG_X86_FEAT_FXSR)) - - -//-- /* +#define VG_X86_SUPPORTED_FEATURES \ + ((1 << VG_X86_FEAT_FPU) | \ + (1 << VG_X86_FEAT_VME) | \ + (1 << VG_X86_FEAT_DE) | \ + (1 << VG_X86_FEAT_PSE) | \ + (1 << VG_X86_FEAT_TSC) | \ + (0 << VG_X86_FEAT_MSR) | \ + (1 << VG_X86_FEAT_PAE) | \ + (1 << VG_X86_FEAT_MCE) | \ + (1 << VG_X86_FEAT_CX8) | \ + (1 << VG_X86_FEAT_APIC) | \ + (0 << VG_X86_FEAT_SEP) | \ + (1 << VG_X86_FEAT_MTRR) | \ + (1 << VG_X86_FEAT_PGE) | \ + (1 << VG_X86_FEAT_MCA) | \ + (1 << VG_X86_FEAT_CMOV) | \ + (1 << VG_X86_FEAT_PAT) | \ + (1 << VG_X86_FEAT_PSE36) | \ + (0 << VG_X86_FEAT_CLFSH) | \ + (1 << VG_X86_FEAT_DS) | \ + (1 << VG_X86_FEAT_ACPI) | \ + (1 << VG_X86_FEAT_MMX) | \ + (1 << VG_X86_FEAT_FXSR) | \ + (1 << VG_X86_FEAT_SSE) | \ + (1 << VG_X86_FEAT_SSE2) | \ + (1 << VG_X86_FEAT_SS) | \ + (1 << VG_X86_FEAT_HT) | \ + (1 << VG_X86_FEAT_TM) | \ + (0 << VG_X86_FEAT_IA64) | \ + (1 << VG_X86_FEAT_PBE)) + +#define VG_AMD_SUPPORTED_FEATURES \ + ((0 << (VG_AMD_FEAT_SYSCALL % 32)) | \ + (0 << (VG_AMD_FEAT_NXP % 32)) | \ + (1 << (VG_AMD_FEAT_MMXEXT % 32)) | \ + (0 << (VG_AMD_FEAT_FFXSR % 32)) | \ + (0 << (VG_AMD_FEAT_LONGMODE % 32)) | \ + (0 << (VG_AMD_FEAT_3DNOWEXT % 32)) | \ + (0 << (VG_AMD_FEAT_3DNOW % 32)) | \ + /* Common bits between standard features and AMD features */ \ + (1 << VG_X86_FEAT_FPU) | \ + (1 << VG_X86_FEAT_VME) | \ + (1 << VG_X86_FEAT_DE) | \ + (1 << VG_X86_FEAT_PSE) | \ + (1 << VG_X86_FEAT_TSC) | \ + (0 << VG_X86_FEAT_MSR) | \ + (1 << VG_X86_FEAT_PAE) | \ + (1 << VG_X86_FEAT_MCE) | \ + (1 << VG_X86_FEAT_CX8) | \ + (1 << VG_X86_FEAT_APIC) | \ + (1 << VG_X86_FEAT_MTRR) | \ + (1 << VG_X86_FEAT_PGE) | \ + (1 << VG_X86_FEAT_MCA) | \ + (1 << VG_X86_FEAT_CMOV) | \ + (1 << VG_X86_FEAT_PAT) | \ + (1 << VG_X86_FEAT_PSE36) | \ + (1 << VG_X86_FEAT_MMX) | \ + (1 << VG_X86_FEAT_FXSR)) + + +//-- /* //-- For simulating the cpuid instruction, we will //-- issue a "real" cpuid instruction and then mask out //-- the bits of the features we do not support currently (3dnow mostly). //-- We also claim to not support most CPUID operations. -//-- +//-- //-- Dirk Mueller //-- //-- http://www.sandpile.org/ia32/cpuid.htm @@ -1146,7 +1152,7 @@ static void helper_SBB ( Int sz, //-- UInt eax, ebx, ecx, edx; //-- //-- if (cpuid_level == -2) -//-- get_cpu_features(); /* for cpu_vendor */ +//-- get_cpu_features(); /* for cpu_vendor */ //-- //-- VG_(cpuid)(op, &eax, &ebx, &ecx, &edx); //-- @@ -1160,7 +1166,7 @@ static void helper_SBB ( Int sz, //-- /* Implement some private information at 0xd8000000 */ //-- static const Char valgrind_vendor[] = "ValgrindVCPU"; //-- -//-- eax = 0xd8000000; /* max request */ +//-- eax = 0xd8000000; /* max request */ //-- ebx = *(UInt *)&valgrind_vendor[0]; //-- ecx = *(UInt *)&valgrind_vendor[8]; //-- edx = *(UInt *)&valgrind_vendor[4]; @@ -1173,20 +1179,20 @@ static void helper_SBB ( Int sz, //-- case VG_CPU_VENDOR_INTEL: //-- switch(op) { //-- case 1: -//-- ecx = 0; /* mask out all extended features for now */ -//-- break; +//-- ecx = 0; /* mask out all extended features for now */ +//-- break; //-- //-- case 0x80000001: -//-- ebx = ecx = edx = 0; -//-- break; +//-- ebx = ecx = edx = 0; +//-- break; //-- } //-- break; //-- //-- case VG_CPU_VENDOR_AMD: //-- switch(op) { //-- case 0x80000001: -//-- edx &= VG_AMD_SUPPORTED_FEATURES; -//-- break; +//-- edx &= VG_AMD_SUPPORTED_FEATURES; +//-- break; //-- } //-- break; //-- } @@ -1352,7 +1358,7 @@ static Char nameISize ( Int size ) //-- case ADC: case SBB: //-- uFlagsRWU(cb, FlagC, FlagsOSZACP, FlagsEmpty); break; //-- case MUL: case UMUL: -//-- uFlagsRWU(cb, FlagsEmpty, FlagsOC, FlagsSZAP); break; +//-- uFlagsRWU(cb, FlagsEmpty, FlagsOC, FlagsSZAP); break; //-- case ADD: case SUB: case NEG: //-- uFlagsRWU(cb, FlagsEmpty, FlagsOSZACP, FlagsEmpty); break; //-- case INC: case DEC: @@ -1497,7 +1503,7 @@ IRTemp disAMode ( Int* len, UChar sorb, UInt delta, UChar* buf ) { UChar rm = mod_reg_rm; DIS(buf, "%s(%s)", sorbTxt(sorb), nameIReg(4,rm)); *len = 1; - return disAMode_copy2tmp( + return disAMode_copy2tmp( handleSegOverride(sorb, getIReg(4,rm))); } @@ -1509,8 +1515,8 @@ IRTemp disAMode ( Int* len, UChar sorb, UInt delta, UChar* buf ) { UChar rm = mod_reg_rm & 7; UInt d = getSDisp8(delta); DIS(buf, "%s%d(%s)", sorbTxt(sorb), d, nameIReg(4,rm)); - *len = 2; - return disAMode_copy2tmp( + *len = 2; + return disAMode_copy2tmp( handleSegOverride(sorb, binop(Iop_Add32,getIReg(4,rm),mkU32(d)))); } @@ -1523,8 +1529,8 @@ IRTemp disAMode ( Int* len, UChar sorb, UInt delta, UChar* buf ) { UChar rm = mod_reg_rm & 7; UInt d = getUDisp32(delta); DIS(buf, "%s0x%x(%s)", sorbTxt(sorb), d, nameIReg(4,rm)); - *len = 5; - return disAMode_copy2tmp( + *len = 5; + return disAMode_copy2tmp( handleSegOverride(sorb, binop(Iop_Add32,getIReg(4,rm),mkU32(d)))); } @@ -1569,16 +1575,16 @@ IRTemp disAMode ( Int* len, UChar sorb, UInt delta, UChar* buf ) UChar scale = (sib >> 6) & 3; UChar index_r = (sib >> 3) & 7; UChar base_r = sib & 7; - delta++; + delta++; if (index_r != R_ESP && base_r != R_EBP) { DIS(buf, "%s(%s,%s,%d)", sorbTxt(sorb), nameIReg(4,base_r), nameIReg(4,index_r), 1< */ - vassert(0); + vassert(0); //-- case 0xA5: - // dis_REP_op ( CondNZ, dis_MOVS, sz, eip_orig, - // guest_eip_bbstart+delta, "repne movs" ); - // break; + // dis_REP_op ( CondNZ, dis_MOVS, sz, eip_orig, + // guest_eip_bbstart+delta, "repne movs" ); + // break; //-- //-- case 0xA6: sz = 1; /* REPNE CMPS */ //-- case 0xA7: @@ -8692,21 +8699,21 @@ static DisResult disInstr ( /*IN*/ Bool resteerOK, ty = szToITy(sz); t1 = newTemp(ty); t2 = newTemp(ty); if (epartIsReg(modrm)) { - assign(t1, getIReg(sz, eregOfRM(modrm))); - assign(t2, getIReg(sz, gregOfRM(modrm))); - putIReg(sz, gregOfRM(modrm), mkexpr(t1)); - putIReg(sz, eregOfRM(modrm), mkexpr(t2)); + assign(t1, getIReg(sz, eregOfRM(modrm))); + assign(t2, getIReg(sz, gregOfRM(modrm))); + putIReg(sz, gregOfRM(modrm), mkexpr(t1)); + putIReg(sz, eregOfRM(modrm), mkexpr(t2)); delta++; DIP("xchg%c %s, %s\n", nameISize(sz), nameIReg(sz,gregOfRM(modrm)), nameIReg(sz,eregOfRM(modrm))); } else { addr = disAMode ( &alen, sorb, delta, dis_buf ); - assign( t1, loadLE(ty,mkexpr(addr)) ); - assign( t2, getIReg(sz,gregOfRM(modrm)) ); - storeLE( mkexpr(addr), mkexpr(t2) ); - putIReg( sz, gregOfRM(modrm), mkexpr(t1) ); - delta += alen; + assign( t1, loadLE(ty,mkexpr(addr)) ); + assign( t2, getIReg(sz,gregOfRM(modrm)) ); + storeLE( mkexpr(addr), mkexpr(t2) ); + putIReg( sz, gregOfRM(modrm), mkexpr(t1) ); + delta += alen; DIP("xchg%c %s, %s\n", nameISize(sz), nameIReg(sz,gregOfRM(modrm)), dis_buf); } @@ -9058,8 +9065,8 @@ static DisResult disInstr ( /*IN*/ Bool resteerOK, break; } -//-- if (!VG_(cpu_has_feature)(VG_X86_FEAT_CPUID)) -//-- goto decode_failure; +//-- if (!VG_(cpu_has_feature)(VG_X86_FEAT_CPUID)) +//-- goto decode_failure; //-- //-- t1 = newTemp(cb); //-- t2 = newTemp(cb); @@ -9210,12 +9217,12 @@ static DisResult disInstr ( /*IN*/ Bool resteerOK, case 0x9D: /* set-GEb/set-NLb (jump greater or equal) */ case 0x9E: /* set-LEb/set-NGb (jump less or equal) */ case 0x9F: /* set-Gb/set-NLEb (jump greater) */ - t1 = newTemp(Ity_I8); - assign( t1, unop(Iop_1Uto8,mk_calculate_condition(opc-0x90)) ); + t1 = newTemp(Ity_I8); + assign( t1, unop(Iop_1Uto8,mk_calculate_condition(opc-0x90)) ); modrm = getIByte(delta); if (epartIsReg(modrm)) { delta++; - putIReg(1, eregOfRM(modrm), mkexpr(t1)); + putIReg(1, eregOfRM(modrm), mkexpr(t1)); DIP("set%s %s\n", name_Condcode(opc-0x90), nameIReg(1,eregOfRM(modrm))); } else { @@ -9331,7 +9338,7 @@ static DisResult disInstr ( /*IN*/ Bool resteerOK, //-- } //-- if (sz == 4) { //-- /* The leading 0x0F is implied for MMX*, so we don't -//-- include it. */ +//-- include it. */ //-- uInstr2(cb, MMX3, 0, //-- Lit16, (((UShort)byte1) << 8) | ((UShort)byte2), //-- Lit16, ((UShort)byte3) ); @@ -9341,7 +9348,7 @@ static DisResult disInstr ( /*IN*/ Bool resteerOK, //-- : subopc == 4 ? "ra" //-- : "??"), //-- nameMMXGran(opc & 3), (Int)byte3, nameMMXReg(mmreg) ); -//-- } else { +//-- } else { //-- /* Whereas we have to include it for SSE. */ //-- uInstr3(cb, SSE5, 0, //-- Lit16, (((UShort)0x66) << 8) | ((UShort)0x0F), @@ -9355,7 +9362,7 @@ static DisResult disInstr ( /*IN*/ Bool resteerOK, //-- : subopc == 7 ? "(PSLLDQ)" //-- : "??"), //-- nameMMXGran(opc & 3), (Int)byte3, nameXMMReg(mmreg) ); -//-- } +//-- } //-- break; //-- } //-- diff --git a/VEX/priv/main/vex_main.c b/VEX/priv/main/vex_main.c index 2ba4e477da..a43fe70c33 100644 --- a/VEX/priv/main/vex_main.c +++ b/VEX/priv/main/vex_main.c @@ -118,6 +118,7 @@ TranslateResult LibVEX_Translate ( /* IN: the block to translate, and its guest address. */ UChar* guest_bytes, Addr64 guest_bytes_addr, + Bool (*chase_into_ok) ( Addr64 ), /* OUT: the number of bytes actually read */ Int* guest_bytes_read, /* IN: a place to put the resulting code, and its size */ @@ -149,7 +150,8 @@ TranslateResult LibVEX_Translate ( void (*ppReg) ( HReg ); HInstrArray* (*iselBB) ( IRBB* ); IRBB* (*bbToIR) ( UChar*, Addr64, Int*, - Bool(*)(Addr64), Bool ); + Bool(*)(Addr64), + Bool(*)(Addr64), Bool ); Int (*emit) ( UChar*, Int, HInstr* ); IRExpr* (*specHelper) ( Char*, IRExpr** ); Bool (*preciseMemExnsFn) ( Int, Int ); @@ -231,6 +233,7 @@ TranslateResult LibVEX_Translate ( guest_bytes_addr, guest_bytes_read, byte_accessible, + chase_into_ok, host_is_bigendian ); if (irbb == NULL) { diff --git a/VEX/pub/libvex.h b/VEX/pub/libvex.h index ee10405fe6..2474cfb160 100644 --- a/VEX/pub/libvex.h +++ b/VEX/pub/libvex.h @@ -140,6 +140,7 @@ TranslateResult LibVEX_Translate ( /* IN: the block to translate, and its guest address. */ UChar* guest_bytes, Addr64 guest_bytes_addr, + Bool (*chase_into_ok) ( Addr64 ), /* OUT: the number of bytes actually read */ Int* guest_bytes_read, /* IN: a place to put the resulting code, and its size */ diff --git a/VEX/test_main.c b/VEX/test_main.c index ef502f46eb..87903c9f42 100644 --- a/VEX/test_main.c +++ b/VEX/test_main.c @@ -51,6 +51,7 @@ static Bool verbose = True; static IRBB* ac_instrument ( IRBB*, VexGuestLayout*, IRType ); static IRBB* mc_instrument ( IRBB*, VexGuestLayout*, IRType ); +static Bool chase_into_not_ok ( Addr64 dst ) { return False; } int main ( int argc, char** argv ) { @@ -75,9 +76,10 @@ int main ( int argc, char** argv ) /* Run with default params. However, we can't allow bb chasing since that causes the front end to get segfaults when it tries - to read code outside the initial BB we hand it. */ + to read code outside the initial BB we hand it. So when calling + LibVEX_Translate, send in a chase-into predicate that always + returns False. */ LibVEX_default_VexControl ( &vcon ); - vcon.guest_chase_thresh = 0; vcon.iropt_level = 2; LibVEX_Init ( &failure_exit, &log_bytes, @@ -120,7 +122,8 @@ int main ( int argc, char** argv ) tres = LibVEX_Translate ( InsnSetX86, InsnSetX86, - origbuf, (Addr64)orig_addr, &orig_used, + origbuf, (Addr64)orig_addr, chase_into_not_ok, + &orig_used, transbuf, N_TRANSBUF, &trans_used, #if 0 /* addrcheck */ ac_instrument, /* instrument1 */