From: Andrew Goodbody Date: Thu, 24 Jul 2025 11:37:38 +0000 (+0100) Subject: clk: stm32: Wrong macros used in register read X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=8693fe92ace46ab537e275899e55924ca82feaae;p=thirdparty%2Fu-boot.git clk: stm32: Wrong macros used in register read Smatch reported a warning about a shift macro being used as a mask. Make the obvious changes to make this register read calculation work the same as the previous ones. Signed-off-by: Andrew Goodbody Reviewed-by: Patrice Chotard --- diff --git a/drivers/clk/stm32/clk-stm32h7.c b/drivers/clk/stm32/clk-stm32h7.c index aa3be414a29..df82db69738 100644 --- a/drivers/clk/stm32/clk-stm32h7.c +++ b/drivers/clk/stm32/clk-stm32h7.c @@ -549,8 +549,8 @@ static u32 stm32_get_PLL1_rate(struct stm32_rcc_regs *regs, divr1 = readl(®s->pll1divr) & RCC_PLL1DIVR_DIVR1_MASK; divr1 = (divr1 >> RCC_PLL1DIVR_DIVR1_SHIFT) + 1; - fracn1 = readl(®s->pll1fracr) & RCC_PLL1DIVR_DIVR1_MASK; - fracn1 = fracn1 & RCC_PLL1DIVR_DIVR1_SHIFT; + fracn1 = readl(®s->pll1fracr) & RCC_PLL1FRACR_FRACN1_MASK; + fracn1 = (fracn1 >> RCC_PLL1FRACR_FRACN1_SHIFT) + 1; vco = (pllsrc / divm1) * divn1; rate = (pllsrc * fracn1) / (divm1 * 8192);