From: Hongren Zheng <i@zenithal.me>
Date: Fri, 26 Apr 2024 06:03:43 +0000 (+0000)
Subject: Implement riscv_vlen_asm for riscv32
X-Git-Tag: openssl-3.4.0-alpha1~568
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=87314d24c4f025df1ebf47dc527cc8a96bef354a;p=thirdparty%2Fopenssl.git

Implement riscv_vlen_asm for riscv32

riscvcap.c: undefined reference to 'riscv_vlen_asm'

Reviewed-by: Paul Dale <ppzgs1@gmail.com>
Reviewed-by: Tomas Mraz <tomas@openssl.org>
(Merged from https://github.com/openssl/openssl/pull/24270)
---

diff --git a/crypto/riscv32cpuid.pl b/crypto/riscv32cpuid.pl
index 20694e7de7e..ac1c043ec91 100644
--- a/crypto/riscv32cpuid.pl
+++ b/crypto/riscv32cpuid.pl
@@ -84,5 +84,22 @@ OPENSSL_cleanse:
 ___
 }
 
+{
+my ($ret) = ('a0');
+$code .= <<___;
+################################################################################
+# size_t riscv_vlen_asm(void)
+# Return VLEN (i.e. the length of a vector register in bits).
+.p2align 3
+.globl riscv_vlen_asm
+.type riscv_vlen_asm,\@function
+riscv_vlen_asm:
+    csrr $ret, vlenb
+    slli $ret, $ret, 3
+    ret
+.size riscv_vlen_asm,.-riscv_vlen_asm
+___
+}
+
 print $code;
 close STDOUT or die "error closing STDOUT: $!";