From: Tvrtko Ursulin Date: Tue, 24 Mar 2026 08:40:09 +0000 (+0000) Subject: drm/xe/xelpg: Limit AuxCCS ring buffer programming to Alderlake X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=88139af77d6acd74bf73f5e36f4bdc63f033f399;p=thirdparty%2Flinux.git drm/xe/xelpg: Limit AuxCCS ring buffer programming to Alderlake At the moment the driver does not support AuxCCS at all due respective modifiers being hidden from userspace. As we are about to start enabling them, starting with Alderlake, let us begin by limiting the ring buffer support to just that initial platform. Signed-off-by: Tvrtko Ursulin Cc: Rodrigo Vivi Reviewed-by: Rodrigo Vivi Link: https://patch.msgid.link/20260324084018.20353-4-tvrtko.ursulin@igalia.com Signed-off-by: Rodrigo Vivi --- diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c index bce7d93ce3a30..92b33925ce08b 100644 --- a/drivers/gpu/drm/xe/xe_ring_ops.c +++ b/drivers/gpu/drm/xe/xe_ring_ops.c @@ -334,9 +334,9 @@ static bool has_aux_ccs(struct xe_device *xe) * PVC is a special case that has no compression of either type * (FlatCCS or AuxCCS). Also, AuxCCS is no longer used from Xe2 * onward, so any future platforms with no FlatCCS will not have - * AuxCCS either. + * AuxCCS, and we explicitly do not want to support it on MTL. */ - if (GRAPHICS_VER(xe) >= 20 || xe->info.platform == XE_PVC) + if (GRAPHICS_VERx100(xe) >= 1270 || xe->info.platform == XE_PVC) return false; return !xe->info.has_flat_ccs;