From: Julian Seward <jseward@acm.org>
Date: Wed, 27 Dec 2006 21:21:14 +0000 (+0000)
Subject: Enable lvxl and stvxl.
X-Git-Tag: svn/VALGRIND_3_3_1^2~71
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=895104e487687bddcf2d4bba14aa5a2f16a351a0;p=thirdparty%2Fvalgrind.git

Enable lvxl and stvxl.


git-svn-id: svn://svn.valgrind.org/vex/trunk@1707
---

diff --git a/VEX/priv/guest-ppc/toIR.c b/VEX/priv/guest-ppc/toIR.c
index f014264618..a1444f86cf 100644
--- a/VEX/priv/guest-ppc/toIR.c
+++ b/VEX/priv/guest-ppc/toIR.c
@@ -6902,10 +6902,9 @@ static Bool dis_av_load ( VexAbiInfo* vbi, UInt theInstr )
       break;
 
    case 0x167: // lvxl (Load Vector Indexed LRU, AV p128)
-     // XXX: lvxl gives explicit control over cache block replacement
       DIP("lvxl v%d,r%u,r%u\n", vD_addr, rA_addr, rB_addr);
-      DIP(" => not implemented\n");
-      return False;
+      putVReg( vD_addr, loadBE(Ity_V128, mkexpr(EA_align16)) );
+      break;
 
    default:
       vex_printf("dis_av_load(ppc)(opc2)\n");
@@ -6990,12 +6989,9 @@ static Bool dis_av_store ( UInt theInstr )
       break;
 
    case 0x1E7: // stvxl (Store Vector Indexed LRU, AV p135)
-     // XXX: stvxl can give explicit control over cache block replacement
       DIP("stvxl v%d,r%u,r%u\n", vS_addr, rA_addr, rB_addr);
-      DIP(" => not implemented\n");
-      return False;
-//      STORE(vS, 16, addr_align( mkexpr(EA), 16 ));
-//      break;
+      storeBE( addr_align( mkexpr(EA), 16 ), mkexpr(vS) );
+      break;
 
    default:
       vex_printf("dis_av_store(ppc)(opc2)\n");