From: Andrew Stubbs <ams@codesourcery.com>
Date: Tue, 25 Jun 2019 09:47:09 +0000 (+0000)
Subject: Fix 64-bit addition in prologue.
X-Git-Tag: releases/gcc-9.2.0~206
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=8abc773747e05f0cd63c6df47476cf901e35ca2f;p=thirdparty%2Fgcc.git

Fix 64-bit addition in prologue.

2019-06-25  Andrew Stubbs  <ams@codesourcery.com>

	Backport from mainline
	2019-05-24  Andrew Stubbs  <ams@codesourcery.com>

	gcc/
	* config/gcn/gcn.c (gcn_expand_prologue): Use gen_addsi3_scalar_carry
	for lo-part.

From-SVN: r272641
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index b2534affc4b5..8e9c869eee4c 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2019-06-25  Andrew Stubbs  <ams@codesourcery.com>
+
+	Backport from mainline
+	2019-05-24  Andrew Stubbs  <ams@codesourcery.com>
+
+	* config/gcn/gcn.c (gcn_expand_prologue): Use gen_addsi3_scalar_carry
+	for lo-part.
+
 2019-06-21  Richard Biener  <rguenther@suse.de>
 
 	PR tree-optimization/90930
diff --git a/gcc/config/gcn/gcn.c b/gcc/config/gcn/gcn.c
index 1dd2ff2d4f0a..f1fad3bb7b5b 100644
--- a/gcc/config/gcn/gcn.c
+++ b/gcc/config/gcn/gcn.c
@@ -2826,9 +2826,9 @@ gcn_expand_prologue ()
       emit_move_insn (fp_lo, gen_rtx_REG (SImode, 0));
       emit_insn (gen_andsi3_scc (fp_hi, gen_rtx_REG (SImode, 1),
 				 gen_int_mode (0xffff, SImode)));
-      emit_insn (gen_addsi3_scc (fp_lo, fp_lo, wave_offset));
-      emit_insn (gen_addcsi3_scalar_zero (fp_hi, fp_hi,
-					  gen_rtx_REG (BImode, SCC_REG)));
+      rtx scc = gen_rtx_REG (BImode, SCC_REG);
+      emit_insn (gen_addsi3_scalar_carry (fp_lo, fp_lo, wave_offset, scc));
+      emit_insn (gen_addcsi3_scalar_zero (fp_hi, fp_hi, scc));
 
       if (sp_adjust > 0)
 	emit_insn (gen_adddi3_scc (sp, fp, gen_int_mode (sp_adjust, DImode)));