From: Cerion Armour-Brown <cerion@valgrind.org>
Date: Wed, 29 Jun 2005 07:59:18 +0000 (+0000)
Subject: Fixed coupla altivec typos
X-Git-Tag: svn/VALGRIND_3_0_1^2~105
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=8b219ed585cb88ff346a113bca38dbd0e2b25bee;p=thirdparty%2Fvalgrind.git

Fixed coupla altivec typos
 - hopefully fixes FC4 build



git-svn-id: svn://svn.valgrind.org/vex/trunk@1229
---

diff --git a/VEX/priv/host-ppc32/hdefs.c b/VEX/priv/host-ppc32/hdefs.c
index f0fb4e74b1..2f82eec528 100644
--- a/VEX/priv/host-ppc32/hdefs.c
+++ b/VEX/priv/host-ppc32/hdefs.c
@@ -1226,21 +1226,18 @@ void ppPPC32Instr ( PPC32Instr* i )
 
    case Pin_AvLdSt: {
       UChar sz = i->Pin.AvLdSt.sz;
-      UChar* str_sz = (sz == 8) ? "eb" :
-                      (sz == 16) ? "eh" :
-                      (sz == 32) ? "ew" : "";
       if (i->Pin.AvLdSt.addr->tag == Pam_IR) {
          vex_printf("{ ");
          ppLoadImm(hregPPC32_GPR30(), i->Pin.AvLdSt.addr->Pam.RR.index);
          vex_printf(" }");
       }
       if (i->Pin.AvLdSt.isLoad) {
-         vex_printf("lv%sx ", str_sz);
+         vex_printf("lv%sx ", sz==8 ? "eb" : sz==16 ? "eh" : sz==32 ? "ew" : "");
          ppHRegPPC32(i->Pin.AvLdSt.reg);
          vex_printf(",");
          ppPPC32AMode(i->Pin.AvLdSt.addr);
       } else {
-         vex_printf("stv%sx ", str_sz);
+         vex_printf("stv%sx ", sz==8 ? "eb" : sz==16 ? "eh" : sz==32 ? "ew" : "");
          ppHRegPPC32(i->Pin.AvLdSt.reg);
          vex_printf(",");
          ppPPC32AMode(i->Pin.AvLdSt.addr);
diff --git a/VEX/priv/host-ppc32/hdefs.h b/VEX/priv/host-ppc32/hdefs.h
index b69c841391..34b287b286 100644
--- a/VEX/priv/host-ppc32/hdefs.h
+++ b/VEX/priv/host-ppc32/hdefs.h
@@ -686,12 +686,12 @@ extern PPC32Instr* PPC32Instr_FpCmp      ( HReg dst, HReg srcL, HReg srcR );
 extern PPC32Instr* PPC32Instr_RdWrLR     ( Bool wrLR, HReg gpr );
 
 extern PPC32Instr* PPC32Instr_AvLdSt     ( Bool isLoad, UChar sz, HReg, PPC32AMode* );
-extern PPC32Instr* PPC32Instr_AvUnary    ( PPC32FpOp op, HReg dst, HReg src );
-extern PPC32Instr* PPC32Instr_AvBinary   ( PPC32FpOp op, HReg dst, HReg srcL, HReg srcR );
-extern PPC32Instr* PPC32Instr_AvBin8x16  ( PPC32FpOp op, HReg dst, HReg srcL, HReg srcR );
-extern PPC32Instr* PPC32Instr_AvBin16x8  ( PPC32FpOp op, HReg dst, HReg srcL, HReg srcR );
-extern PPC32Instr* PPC32Instr_AvBin32x4  ( PPC32FpOp op, HReg dst, HReg srcL, HReg srcR );
-extern PPC32Instr* PPC32Instr_AvBin32Fx4 ( PPC32FpOp op, HReg dst, HReg srcL, HReg srcR );
+extern PPC32Instr* PPC32Instr_AvUnary    ( PPC32AvOp op, HReg dst, HReg src );
+extern PPC32Instr* PPC32Instr_AvBinary   ( PPC32AvOp op, HReg dst, HReg srcL, HReg srcR );
+extern PPC32Instr* PPC32Instr_AvBin8x16  ( PPC32AvOp op, HReg dst, HReg srcL, HReg srcR );
+extern PPC32Instr* PPC32Instr_AvBin16x8  ( PPC32AvOp op, HReg dst, HReg srcL, HReg srcR );
+extern PPC32Instr* PPC32Instr_AvBin32x4  ( PPC32AvOp op, HReg dst, HReg srcL, HReg srcR );
+extern PPC32Instr* PPC32Instr_AvBin32Fx4 ( PPC32AvOp op, HReg dst, HReg srcL, HReg srcR );
 extern PPC32Instr* PPC32Instr_AvPerm     ( HReg ctl, HReg dst, HReg srcL, HReg srcR );
 extern PPC32Instr* PPC32Instr_AvSel      ( HReg ctl, HReg dst, HReg srcL, HReg srcR );
 extern PPC32Instr* PPC32Instr_AvShlDbl   ( UChar shift, HReg dst, HReg srcL, HReg srcR );