From: Ville Syrjälä Date: Wed, 29 Oct 2025 20:42:14 +0000 (+0200) Subject: drm/i915/dram: Sort SKL+ DIMM register bits X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=8c171a9b8c4cb10b1942d3094f94e27c65232cf7;p=thirdparty%2Fkernel%2Flinux.git drm/i915/dram: Sort SKL+ DIMM register bits Use the customary big endian order when defining the SKL/ICL DIMM registers. Signed-off-by: Ville Syrjälä Link: https://patch.msgid.link/20251029204215.12292-3-ville.syrjala@linux.intel.com Reviewed-by: Lucas De Marchi --- diff --git a/drivers/gpu/drm/i915/intel_mchbar_regs.h b/drivers/gpu/drm/i915/intel_mchbar_regs.h index 378dc7c69f7d4..a46a45b9d2e1a 100644 --- a/drivers/gpu/drm/i915/intel_mchbar_regs.h +++ b/drivers/gpu/drm/i915/intel_mchbar_regs.h @@ -161,24 +161,24 @@ #define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C) #define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010) #define SKL_DRAM_S_SHIFT 16 -#define SKL_DRAM_SIZE_MASK REG_GENMASK(5, 0) +#define SKL_DRAM_RANK_MASK REG_GENMASK(10, 10) +#define SKL_DRAM_RANK_1 REG_FIELD_PREP(SKL_DRAM_RANK_MASK, 0) +#define SKL_DRAM_RANK_2 REG_FIELD_PREP(SKL_DRAM_RANK_MASK, 1) #define SKL_DRAM_WIDTH_MASK REG_GENMASK(9, 8) #define SKL_DRAM_WIDTH_X8 REG_FIELD_PREP(SKL_DRAM_WIDTH_MASK, 0) #define SKL_DRAM_WIDTH_X16 REG_FIELD_PREP(SKL_DRAM_WIDTH_MASK, 1) #define SKL_DRAM_WIDTH_X32 REG_FIELD_PREP(SKL_DRAM_WIDTH_MASK, 2) -#define SKL_DRAM_RANK_MASK REG_GENMASK(10, 10) -#define SKL_DRAM_RANK_1 REG_FIELD_PREP(SKL_DRAM_RANK_MASK, 0) -#define SKL_DRAM_RANK_2 REG_FIELD_PREP(SKL_DRAM_RANK_MASK, 1) -#define ICL_DRAM_SIZE_MASK REG_GENMASK(6, 0) -#define ICL_DRAM_WIDTH_MASK REG_GENMASK(8, 7) -#define ICL_DRAM_WIDTH_X8 REG_FIELD_PREP(ICL_DRAM_WIDTH_MASK, 0) -#define ICL_DRAM_WIDTH_X16 REG_FIELD_PREP(ICL_DRAM_WIDTH_MASK, 1) -#define ICL_DRAM_WIDTH_X32 REG_FIELD_PREP(ICL_DRAM_WIDTH_MASK, 2) +#define SKL_DRAM_SIZE_MASK REG_GENMASK(5, 0) #define ICL_DRAM_RANK_MASK REG_GENMASK(10, 9) #define ICL_DRAM_RANK_1 REG_FIELD_PREP(ICL_DRAM_RANK_MASK, 0) #define ICL_DRAM_RANK_2 REG_FIELD_PREP(ICL_DRAM_RANK_MASK, 1) #define ICL_DRAM_RANK_3 REG_FIELD_PREP(ICL_DRAM_RANK_MASK, 2) #define ICL_DRAM_RANK_4 REG_FIELD_PREP(ICL_DRAM_RANK_MASK, 3) +#define ICL_DRAM_WIDTH_MASK REG_GENMASK(8, 7) +#define ICL_DRAM_WIDTH_X8 REG_FIELD_PREP(ICL_DRAM_WIDTH_MASK, 0) +#define ICL_DRAM_WIDTH_X16 REG_FIELD_PREP(ICL_DRAM_WIDTH_MASK, 1) +#define ICL_DRAM_WIDTH_X32 REG_FIELD_PREP(ICL_DRAM_WIDTH_MASK, 2) +#define ICL_DRAM_SIZE_MASK REG_GENMASK(6, 0) #define SA_PERF_STATUS_0_0_0_MCHBAR_PC _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5918) #define DG1_QCLK_RATIO_MASK REG_GENMASK(9, 2)