From: Jeff Law <law@redhat.com>
Date: Tue, 6 May 1997 19:42:17 +0000 (+0000)
Subject:         * mn10300_sim.h: Fix ordering of bits in the PSW.
X-Git-Tag: gdb-4_18-branchpoint~5578
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=8def9220345a634cea86a9cd6599b3f9e6aca5cf;p=thirdparty%2Fbinutils-gdb.git

    * mn10300_sim.h: Fix ordering of bits in the PSW.
---

diff --git a/sim/mn10300/ChangeLog b/sim/mn10300/ChangeLog
index f3280ccd891..51efa7b80d7 100644
--- a/sim/mn10300/ChangeLog
+++ b/sim/mn10300/ChangeLog
@@ -1,5 +1,7 @@
 Tue May  6 13:24:36 1997  Jeffrey A Law  (law@cygnus.com)
 
+	* mn10300_sim.h: Fix ordering of bits in the PSW.
+
 	* interp.c: Improve hashing routine to avoid long list
 	traversals for common instructions.  Add HASH_STAT support.
 	Rewrite opcode dispatch code using a big switch instead of
diff --git a/sim/mn10300/mn10300_sim.h b/sim/mn10300/mn10300_sim.h
index 2fcb85a78f5..40cef234bb4 100644
--- a/sim/mn10300/mn10300_sim.h
+++ b/sim/mn10300/mn10300_sim.h
@@ -72,10 +72,10 @@ extern struct simops Simops[];
 #define PC	(State.regs[9])
 
 #define PSW (State.regs[11])
-#define PSW_V 0x1
-#define PSW_C 0x2
-#define PSW_N 0x4
-#define PSW_Z 0x8
+#define PSW_Z 0x1
+#define PSW_N 0x2
+#define PSW_C 0x4
+#define PSW_V 0x8
 
 #define REG_D0 0
 #define REG_A0 4