From: Midgy BALON Date: Fri, 27 Mar 2026 09:11:28 +0000 (+0100) Subject: arm64: dts: rockchip: rock-3b: Model PI6C20100 as gated-fixed-clock X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=8df9160f6a50dbdae8ec287d429efc9d2d9001bd;p=thirdparty%2Fkernel%2Flinux.git arm64: dts: rockchip: rock-3b: Model PI6C20100 as gated-fixed-clock The Radxa ROCK 3B uses a PI6C20100 PCIe reference clock buffer to provide a 100MHz reference clock to the PCIe 3.0 PHY and controllers. This chip is currently modeled only as a fixed regulator (vcc3v3_pi6c_03), with no clock output representation. The PI6C20100 is a clock generator, not a power supply. Model it properly as a gated-fixed-clock, following the pattern established for the Rock 5 ITX and other boards with similar PCIe clock buffer chips. The gated-fixed-clock node references the regulator as its vdd-supply, allowing the regulator to be enabled on demand. Remove the regulator-always-on and regulator-boot-on properties from vcc3v3_pi6c_03 since the clock framework will manage the regulator lifecycle via vdd-supply. The pcie3x2 node is updated to include the pipe and reference clocks, matching the approach used in rk3588-rock-5-itx.dts. Assisted-by: Claude:claude-3-opus Signed-off-by: Midgy BALON Link: https://patch.msgid.link/20260327091128.2458-1-midgy971@gmail.com Signed-off-by: Heiko Stuebner --- diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts index 69001e453732e..149a5306bb032 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts @@ -56,7 +56,15 @@ }; }; - /* pi6c pcie clock generator */ + /* PI6C20100 PCIe reference clock buffer */ + pcie30_refclk: pcie-clock-generator { + compatible = "gated-fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "pcie30_refclk"; + vdd-supply = <&vcc3v3_pi6c_03>; + }; + vcc3v3_pi6c_03: regulator-3v3-vcc-pi6c-03 { compatible = "regulator-fixed"; enable-active-high; @@ -64,8 +72,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pcie_pwren_h>; regulator-name = "vcc3v3_pi6c_03"; - regulator-always-on; - regulator-boot-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; startup-delay-us = <10000>; @@ -553,6 +559,14 @@ }; &pcie3x2 { + clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, + <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, + <&cru CLK_PCIE30X2_AUX_NDFT>, + <&cru CLK_PCIE30X2_PIPE_DFT>, + <&pcie30_refclk>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux", + "pipe", "ref"; pinctrl-names = "default"; pinctrl-0 = <&pcie30x2m1_pins>; reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;