From: Paul Kocialkowski Date: Mon, 7 Jul 2025 16:51:55 +0000 (+0200) Subject: arm64: dts: allwinner: a133-liontron-h-a133l: Add Ethernet support X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=8f128f357dfe5907a6f3432ffb1f444e93f1fbf2;p=thirdparty%2Flinux.git arm64: dts: allwinner: a133-liontron-h-a133l: Add Ethernet support The Liontron H-A133L board features an Ethernet controller with a JLSemi JL1101 PHY. Its reset pin is tied to the PH12 GPIO. Note that the reset pin must be handled as a bus-wide reset GPIO in order to let the MDIO core properly reset it before trying to read its identification registers. There's no other device on the MDIO bus. The datasheet of the PHY mentions that the reset signal must be held for 1 ms to take effect. Make it 2 ms (and the same for post-delay) to be on the safe side without wasting too much time during boot. Signed-off-by: Paul Kocialkowski Reviewed-by: Andre Przywara Tested-by: Andre Przywara Link: https://patch.msgid.link/20250707165155.581579-5-paulk@sys-base.io Signed-off-by: Chen-Yu Tsai --- diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a133-liontron-h-a133l.dts b/arch/arm64/boot/dts/allwinner/sun50i-a133-liontron-h-a133l.dts index fe77178d3e33e..90a50910f07b7 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a133-liontron-h-a133l.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a133-liontron-h-a133l.dts @@ -65,6 +65,25 @@ status = "okay"; }; +&emac0 { + pinctrl-names = "default"; + pinctrl-0 = <&rmii0_pins>; + phy-handle = <&rmii_phy>; + phy-mode = "rmii"; + status = "okay"; +}; + +&mdio0 { + reset-gpios = <&pio 7 12 GPIO_ACTIVE_LOW>; /* PH12 */ + reset-delay-us = <2000>; + reset-post-delay-us = <2000>; + + rmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + &mmc0 { vmmc-supply = <®_dcdc1>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */