From: Andreas Schwab <schwab@suse.de>
Date: Tue, 8 Jul 2025 13:32:17 +0000 (-0600)
Subject: [PATCH] riscv: allow zero in zacas subword atomic cas
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=8f93b00a241a242677a901812f1a12e8960a5dc2;p=thirdparty%2Fgcc.git

[PATCH] riscv: allow zero in zacas subword atomic cas

gcc:
	PR target/120995
	* config/riscv/sync.md (zacas_atomic_cas_value_strong<mode>):
	Allow op3 to be zero.

gcc/testsuite:
	PR target/120995
	* gcc.target/riscv/amo/zabha-zacas-atomic-cas.c: New test.

(cherry picked from commit 3fd638a9e5497dfdf00f1783d6e704af03fb44b0)
---

diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
index 726800a96623..22acf0850f67 100644
--- a/gcc/config/riscv/sync.md
+++ b/gcc/config/riscv/sync.md
@@ -628,7 +628,7 @@
 	(match_operand:SHORT 1 "memory_operand" "+A"))				;; memory
    (set (match_dup 1)
 	(unspec_volatile:SHORT [(match_operand:SHORT 2 "register_operand" "0")  ;; expected_val
-				(match_operand:SHORT 3 "register_operand" "rJ") ;; desired_val
+				(match_operand:SHORT 3 "reg_or_0_operand" "rJ") ;; desired_val
 				(match_operand:SI 4 "const_int_operand")	;; mod_s
 				(match_operand:SI 5 "const_int_operand")]	;; mod_f
 	 UNSPEC_COMPARE_AND_SWAP))]
diff --git a/gcc/testsuite/gcc.target/riscv/amo/zabha-zacas-atomic-cas.c b/gcc/testsuite/gcc.target/riscv/amo/zabha-zacas-atomic-cas.c
new file mode 100644
index 000000000000..d3d84fd30882
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo/zabha-zacas-atomic-cas.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* PR target/120995 ICE unrecognized subword atomic cas */
+/* { dg-options "-O" } */
+/* { dg-add-options riscv_zacas } */
+/* { dg-add-options riscv_zabha } */
+
+_Bool b;
+void atomic_bool_cmpxchg()
+{
+  __sync_bool_compare_and_swap(&b, 1, 0);
+}