From: Lehua Ding Date: Thu, 17 Aug 2023 11:37:17 +0000 (+0800) Subject: RISC-V: Fix XPASS slp testcases X-Git-Tag: basepoints/gcc-15~6854 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=903d937569992a885faf8a1bf7d120e9e66f456b;p=thirdparty%2Fgcc.git RISC-V: Fix XPASS slp testcases This patch fixs XPASS slp testcases on trunk by making the conditions for xfail stricter. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/partial/slp-1.c: Fix. * gcc.target/riscv/rvv/autovec/partial/slp-16.c: Ditto. * gcc.target/riscv/rvv/autovec/partial/slp-17.c: Ditto. * gcc.target/riscv/rvv/autovec/partial/slp-18.c: Ditto. * gcc.target/riscv/rvv/autovec/partial/slp-19.c: Ditto. * gcc.target/riscv/rvv/autovec/partial/slp-2.c: Ditto. * gcc.target/riscv/rvv/autovec/partial/slp-3.c: Ditto. * gcc.target/riscv/rvv/autovec/partial/slp-4.c: Ditto. * gcc.target/riscv/rvv/autovec/partial/slp-5.c: Ditto. * gcc.target/riscv/rvv/autovec/partial/slp-6.c: Ditto. --- diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c index 788e0450b47b..3571a325f73a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c @@ -19,7 +19,8 @@ f (int8_t *restrict a, int8_t *restrict b, int n) } } -/* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen instead of SLP. */ -/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail *-*-* } } } */ -/* { dg-final { scan-assembler {\tvid\.v} { xfail *-*-* } } } */ -/* { dg-final { scan-assembler {\tvand} { xfail *-*-* } } } */ +/* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen + instead of SLP when riscv-autovec-lmul=m1 or m2. */ +/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } } } */ +/* { dg-final { scan-assembler {\tvid\.v} { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } } } */ +/* { dg-final { scan-assembler {\tvand} { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c index b58e270eaa49..8c5c65152c83 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c @@ -19,7 +19,8 @@ f (uint8_t *restrict a, uint8_t *restrict b, int n) } } -/* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen instead of SLP. */ -/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail *-*-* } } } */ -/* { dg-final { scan-assembler {\tvid\.v} { xfail *-*-* } } } */ +/* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen + instead of SLP when riscv-autovec-lmul=m1 or m2. */ +/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } } } */ +/* { dg-final { scan-assembler {\tvid\.v} { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } } } */ /* { dg-final { scan-assembler-not {\tvmul} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.c index bccf3e6570a4..67dbadafc48c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.c @@ -29,7 +29,8 @@ f (uint8_t *restrict a, uint8_t *restrict b, } } -/* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen instead of SLP. */ -/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 2 "optimized" { xfail *-*-* } } } */ -/* { dg-final { scan-assembler {\tvid\.v} { xfail *-*-* } } } */ +/* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen + instead of SLP when riscv-autovec-lmul=m1. */ +/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 2 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" } } } } */ +/* { dg-final { scan-assembler {\tvid\.v} { xfail { any-opts "--param riscv-autovec-lmul=m1" } } } } */ /* { dg-final { scan-assembler-not {\tvmul} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-18.c index f00bece14143..6e60dabb85f8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-18.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-18.c @@ -21,7 +21,8 @@ f (float *restrict a, float *restrict b, } } -/* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen instead of SLP. */ -/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail *-*-* } } } */ -/* { dg-final { scan-assembler {\tvid\.v} { xfail *-*-* } } } */ +/* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen + instead of SLP when riscv-autovec-lmul=m1 or m2. */ +/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 2 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } } } */ +/* { dg-final { scan-assembler {\tvid\.v} { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } } } */ /* { dg-final { scan-assembler-not {\tvmul} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-19.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-19.c index 67db75517c34..309c30e47356 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-19.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-19.c @@ -21,6 +21,8 @@ f (float *restrict a, float *restrict b, } } -/* { dg-final { scan-tree-dump "\.VEC_PERM" "optimized" { xfail *-*-* } } } */ -/* { dg-final { scan-assembler {\tvid\.v} { xfail *-*-* } } } */ +/* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen + instead of SLP when riscv-autovec-lmul=m1 or m2. */ +/* { dg-final { scan-tree-dump "\.VEC_PERM" "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } } } */ +/* { dg-final { scan-assembler {\tvid\.v} { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } } } */ /* { dg-final { scan-assembler-not {\tvmul} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-2.c index ad60b11d8156..5605b1ba6846 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-2.c @@ -19,5 +19,6 @@ f (int16_t *restrict a, int16_t *restrict b, int n) } } -/* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen instead of SLP. */ -/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail *-*-* } } } */ +/* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen + instead of SLP when riscv-autovec-lmul=m1. */ +/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c index 088828f326fd..fde54e1f059b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c @@ -19,5 +19,6 @@ f (int8_t *restrict a, int8_t *restrict b, int n) } } -/* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen instead of SLP. */ -/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail *-*-* } } } */ +/* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen + instead of SLP when riscv-autovec-lmul=m1 or m2. */ +/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-4.c index d56feeb8fdfb..e18ebd3ae2fb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-4.c @@ -19,5 +19,6 @@ f (int16_t *restrict a, int16_t *restrict b, int n) } } -/* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen instead of SLP. */ -/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail *-*-* } } } */ +/* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen + instead of SLP when riscv-autovec-lmul=m1. */ +/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c index d825a257ccdc..600699be9d12 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c @@ -19,5 +19,6 @@ f (int8_t *restrict a, int8_t *restrict b, int n) } } -/* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen instead of SLP. */ -/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail *-*-* } } } */ +/* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen + instead of SLP when riscv-autovec-lmul=m1 or m2. */ +/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-6.c index 160880c42b78..9fca6bdf5d02 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-6.c @@ -19,6 +19,7 @@ f (uint8_t *restrict a, uint8_t *restrict b, int n) } } -/* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen instead of SLP. */ -/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail *-*-* } } } */ +/* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen + instead of SLP when riscv-autovec-lmul=m1. */ +/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" } } } } */