From: Uros Bizjak Date: Sun, 31 Jul 2011 18:23:40 +0000 (+0200) Subject: re PR target/49920 (unable to find a register to spill in class ‘DIREG’) X-Git-Tag: releases/gcc-4.4.7~294 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=90ad61d4db4d34b3531786a94a67257a3a618942;p=thirdparty%2Fgcc.git re PR target/49920 (unable to find a register to spill in class ‘DIREG’) PR target/49920 * config/i386/i386.md (strset): Do not expand strset_singleop when %eax or $edi are fixed. (*strsetdi_rex_1): Disable when %eax or %edi are fixed. (*strsetsi_1): Ditto. (*strsetsi_rex_1): Ditto. (*strsethi_1): Ditto. (*strsethi_rex_1): Ditto. (*strsetqi_1): Ditto. (*strsetqi_rex_1): Ditto. (*rep_stosdi_rex64): Disable when %eax, %ecx or %edi are fixed. (*rep_stossi): Ditto. (*rep_stossi_rex64): Ditto. (*rep_stosqi): Ditto. (*rep_stosqi_rex64): Ditto. (*strlenqi_1): Ditto. (*strlenqi_rex_1): Ditto. (cmpstrnsi): Also fail when %ecx is fixed. (*cmpstrnqi_nz_1): Disable when %ecx, %esi or %edi are fixed. (*cmpstrnqi_nz_rex_1): Ditto. (*cmpstrnqi_1): Ditto. (*cmpstrnqi_rex_1): Ditto. (*strmovdi_rex_1): Disable when %esi or %edi are fixed. (*strmovsi_1): Ditto. (*strmovsi_rex_1): Ditto. (*strmovhi_1): Ditto. (*strmovhi_rex_1): Ditto. (*strmovqi_1): Ditto. (*strmovqi_rex_1): Ditto. (*rep_movdi_rex64): Disable when %ecx, %esi or %edi are fixed. (*rep_movsi): Ditto. (*rep_movsi_rex64): Ditto. (*rep_movqi): Ditto. (*rep_movqi_rex64): Ditto. testsuite/ChangeLog: PR target/49920 * gcc.target/i386/pr49920.c: New test. From-SVN: r176983 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7adb7aed1461..f99572671931 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,38 @@ + PR target/49920 + * config/i386/i386.md (strset): Do not expand strset_singleop + when %eax or $edi are fixed. + (*strsetdi_rex_1): Disable when %eax or %edi are fixed. + (*strsetsi_1): Ditto. + (*strsetsi_rex_1): Ditto. + (*strsethi_1): Ditto. + (*strsethi_rex_1): Ditto. + (*strsetqi_1): Ditto. + (*strsetqi_rex_1): Ditto. + (*rep_stosdi_rex64): Disable when %eax, %ecx or %edi are fixed. + (*rep_stossi): Ditto. + (*rep_stossi_rex64): Ditto. + (*rep_stosqi): Ditto. + (*rep_stosqi_rex64): Ditto. + (*strlenqi_1): Ditto. + (*strlenqi_rex_1): Ditto. + (cmpstrnsi): Also fail when %ecx is fixed. + (*cmpstrnqi_nz_1): Disable when %ecx, %esi or %edi are fixed. + (*cmpstrnqi_nz_rex_1): Ditto. + (*cmpstrnqi_1): Ditto. + (*cmpstrnqi_rex_1): Ditto. + (*strmovdi_rex_1): Disable when %esi or %edi are fixed. + (*strmovsi_1): Ditto. + (*strmovsi_rex_1): Ditto. + (*strmovhi_1): Ditto. + (*strmovhi_rex_1): Ditto. + (*strmovqi_1): Ditto. + (*strmovqi_rex_1): Ditto. + (*rep_movdi_rex64): Disable when %ecx, %esi or %edi are fixed. + (*rep_movsi): Ditto. + (*rep_movsi_rex64): Ditto. + (*rep_movqi): Ditto. + (*rep_movqi_rex64): Ditto. + 2011-07-28 Uros Bizjak PR target/47364 diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 2298b746fe87..1de7b3a3a5e3 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -19018,7 +19018,8 @@ (set (match_operand:DI 1 "register_operand" "=S") (plus:DI (match_dup 3) (const_int 8)))] - "TARGET_64BIT" + "TARGET_64BIT + && !(fixed_regs[SI_REG] || fixed_regs[DI_REG])" "movsq" [(set_attr "type" "str") (set_attr "mode" "DI") @@ -19033,7 +19034,8 @@ (set (match_operand:SI 1 "register_operand" "=S") (plus:SI (match_dup 3) (const_int 4)))] - "!TARGET_64BIT" + "!TARGET_64BIT + && !(fixed_regs[SI_REG] || fixed_regs[DI_REG])" "movs{l|d}" [(set_attr "type" "str") (set_attr "mode" "SI") @@ -19048,7 +19050,8 @@ (set (match_operand:DI 1 "register_operand" "=S") (plus:DI (match_dup 3) (const_int 4)))] - "TARGET_64BIT" + "TARGET_64BIT + && !(fixed_regs[SI_REG] || fixed_regs[DI_REG])" "movs{l|d}" [(set_attr "type" "str") (set_attr "mode" "SI") @@ -19063,7 +19066,8 @@ (set (match_operand:SI 1 "register_operand" "=S") (plus:SI (match_dup 3) (const_int 2)))] - "!TARGET_64BIT" + "!TARGET_64BIT + && !(fixed_regs[SI_REG] || fixed_regs[DI_REG])" "movsw" [(set_attr "type" "str") (set_attr "memory" "both") @@ -19078,7 +19082,8 @@ (set (match_operand:DI 1 "register_operand" "=S") (plus:DI (match_dup 3) (const_int 2)))] - "TARGET_64BIT" + "TARGET_64BIT + && !(fixed_regs[SI_REG] || fixed_regs[DI_REG])" "movsw" [(set_attr "type" "str") (set_attr "memory" "both") @@ -19093,7 +19098,8 @@ (set (match_operand:SI 1 "register_operand" "=S") (plus:SI (match_dup 3) (const_int 1)))] - "!TARGET_64BIT" + "!TARGET_64BIT + && !(fixed_regs[SI_REG] || fixed_regs[DI_REG])" "movsb" [(set_attr "type" "str") (set_attr "memory" "both") @@ -19108,7 +19114,8 @@ (set (match_operand:DI 1 "register_operand" "=S") (plus:DI (match_dup 3) (const_int 1)))] - "TARGET_64BIT" + "TARGET_64BIT + && !(fixed_regs[SI_REG] || fixed_regs[DI_REG])" "movsb" [(set_attr "type" "str") (set_attr "memory" "both") @@ -19138,7 +19145,8 @@ (set (mem:BLK (match_dup 3)) (mem:BLK (match_dup 4))) (use (match_dup 5))] - "TARGET_64BIT" + "TARGET_64BIT + && !(fixed_regs[CX_REG] || fixed_regs[SI_REG] || fixed_regs[DI_REG])" "rep{%;} movsq" [(set_attr "type" "str") (set_attr "prefix_rep" "1") @@ -19157,7 +19165,8 @@ (set (mem:BLK (match_dup 3)) (mem:BLK (match_dup 4))) (use (match_dup 5))] - "!TARGET_64BIT" + "!TARGET_64BIT + && !(fixed_regs[CX_REG] || fixed_regs[SI_REG] || fixed_regs[DI_REG])" "rep{%;} movs{l|d}" [(set_attr "type" "str") (set_attr "prefix_rep" "1") @@ -19176,7 +19185,8 @@ (set (mem:BLK (match_dup 3)) (mem:BLK (match_dup 4))) (use (match_dup 5))] - "TARGET_64BIT" + "TARGET_64BIT + && !(fixed_regs[CX_REG] || fixed_regs[SI_REG] || fixed_regs[DI_REG])" "rep{%;} movs{l|d}" [(set_attr "type" "str") (set_attr "prefix_rep" "1") @@ -19193,7 +19203,8 @@ (set (mem:BLK (match_dup 3)) (mem:BLK (match_dup 4))) (use (match_dup 5))] - "!TARGET_64BIT" + "!TARGET_64BIT + && !(fixed_regs[CX_REG] || fixed_regs[SI_REG] || fixed_regs[DI_REG])" "rep{%;} movsb" [(set_attr "type" "str") (set_attr "prefix_rep" "1") @@ -19210,7 +19221,8 @@ (set (mem:BLK (match_dup 3)) (mem:BLK (match_dup 4))) (use (match_dup 5))] - "TARGET_64BIT" + "TARGET_64BIT + && !(fixed_regs[CX_REG] || fixed_regs[SI_REG] || fixed_regs[DI_REG])" "rep{%;} movsb" [(set_attr "type" "str") (set_attr "prefix_rep" "1") @@ -19270,7 +19282,9 @@ operands[3] = gen_rtx_PLUS (Pmode, operands[0], GEN_INT (GET_MODE_SIZE (GET_MODE (operands[2])))); - if (TARGET_SINGLE_STRINGOP || optimize_insn_for_size_p ()) + /* Can't use this if the user has appropriated eax or edi. */ + if ((TARGET_SINGLE_STRINGOP || optimize_insn_for_size_p ()) + && !(fixed_regs[AX_REG] || fixed_regs[DI_REG])) { emit_insn (gen_strset_singleop (operands[0], operands[1], operands[2], operands[3])); @@ -19292,7 +19306,8 @@ (set (match_operand:DI 0 "register_operand" "=D") (plus:DI (match_dup 1) (const_int 8)))] - "TARGET_64BIT" + "TARGET_64BIT + && !(fixed_regs[AX_REG] || fixed_regs[DI_REG])" "stosq" [(set_attr "type" "str") (set_attr "memory" "store") @@ -19304,7 +19319,8 @@ (set (match_operand:SI 0 "register_operand" "=D") (plus:SI (match_dup 1) (const_int 4)))] - "!TARGET_64BIT" + "!TARGET_64BIT + && !(fixed_regs[AX_REG] || fixed_regs[DI_REG])" "stos{l|d}" [(set_attr "type" "str") (set_attr "memory" "store") @@ -19316,7 +19332,8 @@ (set (match_operand:DI 0 "register_operand" "=D") (plus:DI (match_dup 1) (const_int 4)))] - "TARGET_64BIT" + "TARGET_64BIT + && !(fixed_regs[AX_REG] || fixed_regs[DI_REG])" "stos{l|d}" [(set_attr "type" "str") (set_attr "memory" "store") @@ -19328,7 +19345,8 @@ (set (match_operand:SI 0 "register_operand" "=D") (plus:SI (match_dup 1) (const_int 2)))] - "!TARGET_64BIT" + "!TARGET_64BIT + && !(fixed_regs[AX_REG] || fixed_regs[DI_REG])" "stosw" [(set_attr "type" "str") (set_attr "memory" "store") @@ -19340,7 +19358,8 @@ (set (match_operand:DI 0 "register_operand" "=D") (plus:DI (match_dup 1) (const_int 2)))] - "TARGET_64BIT" + "TARGET_64BIT + && !(fixed_regs[AX_REG] || fixed_regs[DI_REG])" "stosw" [(set_attr "type" "str") (set_attr "memory" "store") @@ -19352,7 +19371,8 @@ (set (match_operand:SI 0 "register_operand" "=D") (plus:SI (match_dup 1) (const_int 1)))] - "!TARGET_64BIT" + "!TARGET_64BIT + && !(fixed_regs[AX_REG] || fixed_regs[DI_REG])" "stosb" [(set_attr "type" "str") (set_attr "memory" "store") @@ -19364,7 +19384,8 @@ (set (match_operand:DI 0 "register_operand" "=D") (plus:DI (match_dup 1) (const_int 1)))] - "TARGET_64BIT" + "TARGET_64BIT + && !(fixed_regs[AX_REG] || fixed_regs[DI_REG])" "stosb" [(set_attr "type" "str") (set_attr "memory" "store") @@ -19390,7 +19411,8 @@ (const_int 0)) (use (match_operand:DI 2 "register_operand" "a")) (use (match_dup 4))] - "TARGET_64BIT" + "TARGET_64BIT + && !(fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])" "rep{%;} stosq" [(set_attr "type" "str") (set_attr "prefix_rep" "1") @@ -19407,7 +19429,8 @@ (const_int 0)) (use (match_operand:SI 2 "register_operand" "a")) (use (match_dup 4))] - "!TARGET_64BIT" + "!TARGET_64BIT + && !(fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])" "rep{%;} stos{l|d}" [(set_attr "type" "str") (set_attr "prefix_rep" "1") @@ -19424,7 +19447,8 @@ (const_int 0)) (use (match_operand:SI 2 "register_operand" "a")) (use (match_dup 4))] - "TARGET_64BIT" + "TARGET_64BIT + && !(fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])" "rep{%;} stos{l|d}" [(set_attr "type" "str") (set_attr "prefix_rep" "1") @@ -19440,7 +19464,8 @@ (const_int 0)) (use (match_operand:QI 2 "register_operand" "a")) (use (match_dup 4))] - "!TARGET_64BIT" + "!TARGET_64BIT + && !(fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])" "rep{%;} stosb" [(set_attr "type" "str") (set_attr "prefix_rep" "1") @@ -19456,7 +19481,8 @@ (const_int 0)) (use (match_operand:QI 2 "register_operand" "a")) (use (match_dup 4))] - "TARGET_64BIT" + "TARGET_64BIT + && !(fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])" "rep{%;} stosb" [(set_attr "type" "str") (set_attr "prefix_rep" "1") @@ -19476,8 +19502,8 @@ if (optimize_insn_for_size_p () && !TARGET_INLINE_ALL_STRINGOPS) FAIL; - /* Can't use this if the user has appropriated esi or edi. */ - if (fixed_regs[SI_REG] || fixed_regs[DI_REG]) + /* Can't use this if the user has appropriated ecx, esi or edi. */ + if (fixed_regs[CX_REG] || fixed_regs[SI_REG] || fixed_regs[DI_REG]) FAIL; out = operands[0]; @@ -19568,7 +19594,8 @@ (clobber (match_operand:SI 0 "register_operand" "=S")) (clobber (match_operand:SI 1 "register_operand" "=D")) (clobber (match_operand:SI 2 "register_operand" "=c"))] - "!TARGET_64BIT" + "!TARGET_64BIT + && !(fixed_regs[CX_REG] || fixed_regs[SI_REG] || fixed_regs[DI_REG])" "repz{%;} cmpsb" [(set_attr "type" "str") (set_attr "mode" "QI") @@ -19583,7 +19610,8 @@ (clobber (match_operand:DI 0 "register_operand" "=S")) (clobber (match_operand:DI 1 "register_operand" "=D")) (clobber (match_operand:DI 2 "register_operand" "=c"))] - "TARGET_64BIT" + "TARGET_64BIT + && !(fixed_regs[CX_REG] || fixed_regs[SI_REG] || fixed_regs[DI_REG])" "repz{%;} cmpsb" [(set_attr "type" "str") (set_attr "mode" "QI") @@ -19618,7 +19646,8 @@ (clobber (match_operand:SI 0 "register_operand" "=S")) (clobber (match_operand:SI 1 "register_operand" "=D")) (clobber (match_operand:SI 2 "register_operand" "=c"))] - "!TARGET_64BIT" + "!TARGET_64BIT + && !(fixed_regs[CX_REG] || fixed_regs[SI_REG] || fixed_regs[DI_REG])" "repz{%;} cmpsb" [(set_attr "type" "str") (set_attr "mode" "QI") @@ -19636,7 +19665,8 @@ (clobber (match_operand:DI 0 "register_operand" "=S")) (clobber (match_operand:DI 1 "register_operand" "=D")) (clobber (match_operand:DI 2 "register_operand" "=c"))] - "TARGET_64BIT" + "TARGET_64BIT + && !(fixed_regs[CX_REG] || fixed_regs[SI_REG] || fixed_regs[DI_REG])" "repz{%;} cmpsb" [(set_attr "type" "str") (set_attr "mode" "QI") @@ -19683,7 +19713,8 @@ (match_operand:SI 4 "register_operand" "0")] UNSPEC_SCAS)) (clobber (match_operand:SI 1 "register_operand" "=D")) (clobber (reg:CC FLAGS_REG))] - "!TARGET_64BIT" + "!TARGET_64BIT + && !(fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])" "repnz{%;} scasb" [(set_attr "type" "str") (set_attr "mode" "QI") @@ -19697,7 +19728,8 @@ (match_operand:DI 4 "register_operand" "0")] UNSPEC_SCAS)) (clobber (match_operand:DI 1 "register_operand" "=D")) (clobber (reg:CC FLAGS_REG))] - "TARGET_64BIT" + "TARGET_64BIT + && !(fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])" "repnz{%;} scasb" [(set_attr "type" "str") (set_attr "mode" "QI") diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 2f0baf5443ce..05aaf2940221 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2011-07-31 Uros Bizjak + + PR target/49920 + * gcc.target/i386/pr49920.c: New test. + 2011-07-28 Tobias Burnus Backported from mainline diff --git a/gcc/testsuite/gcc.target/i386/pr49920.c b/gcc/testsuite/gcc.target/i386/pr49920.c new file mode 100644 index 000000000000..416e7a478471 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr49920.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target ilp32 } */ + +typedef __SIZE_TYPE__ size_t; +extern void *malloc (size_t); + +register unsigned int MR_mr0 asm ("esi"); +register unsigned int MR_mr1 asm ("edi"); + +void ml_backend__ml_closure_gen_module11 (void) +{ + unsigned int MR_tempr1, MR_tempr2, MR_tempr3; + + MR_tempr1 = (unsigned int)((char *) malloc (sizeof (unsigned int)) + 4); + MR_tempr3 = ((unsigned int *) MR_mr0)[0]; + + ((unsigned int *) (MR_tempr1 - 4))[0] = MR_tempr3; + + MR_tempr2 = (unsigned int)((char *) malloc (2 * sizeof (unsigned int))); + + ((unsigned int *) MR_tempr2)[1] = MR_tempr1; +}