From: Petar Jovanovic Date: Mon, 9 Oct 2017 15:48:48 +0000 (+0200) Subject: mips: new Iops added to support MSA X-Git-Tag: VALGRIND_3_14_0~221 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=91373819a398722105111dab58e88dca21279cef;p=thirdparty%2Fvalgrind.git mips: new Iops added to support MSA New Iops are defined: Iop_Scale2_32Fx4, Iop_Scale2_64Fx2, Iop_Log2_32Fx4, Iop_Log2_64Fx2, Iop_F32x4_2toQ16x8, Iop_F64x2_2toQ32x4, Iop_PackOddLanes8x16, Iop_PackEvenLanes8x16, Iop_PackOddLanes16x8, Iop_PackEvenLanes16x8, Iop_PackOddLanes32x4, Iop_PackEvenLanes32x4. Contributed by: Tamara Vlahovic, Aleksandar Rikalo and Aleksandra Karadzic. Related BZ issue - #382563. --- diff --git a/VEX/priv/ir_defs.c b/VEX/priv/ir_defs.c index 8822800f11..61ff837fc1 100644 --- a/VEX/priv/ir_defs.c +++ b/VEX/priv/ir_defs.c @@ -690,6 +690,11 @@ void ppIROp ( IROp op ) case Iop_Sqrt64F0x2: vex_printf("Sqrt64F0x2"); return; case Iop_Sqrt32Fx8: vex_printf("Sqrt32Fx8"); return; case Iop_Sqrt64Fx4: vex_printf("Sqrt64Fx4"); return; + + case Iop_Scale2_32Fx4: vex_printf("Scale2_32Fx4"); return; + case Iop_Scale2_64Fx2: vex_printf("Scale2_64Fx2"); return; + case Iop_Log2_32Fx4: vex_printf("Log2_32Fx4"); return; + case Iop_Log2_64Fx2: vex_printf("Log2_64Fx2"); return; case Iop_Sub32Fx4: vex_printf("Sub32Fx4"); return; case Iop_Sub32Fx2: vex_printf("Sub32Fx2"); return; @@ -724,6 +729,9 @@ void ppIROp ( IROp op ) case Iop_Neg32Fx4: vex_printf("Neg32Fx4"); return; case Iop_Neg32Fx2: vex_printf("Neg32Fx2"); return; + case Iop_F32x4_2toQ16x8: vex_printf("F32x4_2toQ16x8"); return; + case Iop_F64x2_2toQ32x4: vex_printf("F64x2_2toQ32x4"); return; + case Iop_V128to64: vex_printf("V128to64"); return; case Iop_V128HIto64: vex_printf("V128HIto64"); return; case Iop_64HLtoV128: vex_printf("64HLtoV128"); return; @@ -1071,6 +1079,12 @@ void ppIROp ( IROp op ) case Iop_InterleaveEvenLanes8x16: vex_printf("InterleaveEvenLanes8x16"); return; case Iop_InterleaveEvenLanes16x8: vex_printf("InterleaveEvenLanes16x8"); return; case Iop_InterleaveEvenLanes32x4: vex_printf("InterleaveEvenLanes32x4"); return; + case Iop_PackOddLanes8x16: vex_printf("InterleavePackOddLanes8x16"); return; + case Iop_PackOddLanes16x8: vex_printf("InterleavePackOddLanes16x8"); return; + case Iop_PackOddLanes32x4: vex_printf("InterleavePackOddLanes32x4"); return; + case Iop_PackEvenLanes8x16: vex_printf("InterleavePackEvenLanes8x16"); return; + case Iop_PackEvenLanes16x8: vex_printf("InterleavePackEvenLanes16x8"); return; + case Iop_PackEvenLanes32x4: vex_printf("InterleavePackEvenLanes32x4"); return; case Iop_GetElem8x16: vex_printf("GetElem8x16"); return; case Iop_GetElem16x8: vex_printf("GetElem16x8"); return; @@ -2947,6 +2961,13 @@ void typeOfPrimop ( IROp op, case Iop_64HLtoV128: BINARY(Ity_I64,Ity_I64, Ity_V128); + case Iop_Scale2_32Fx4: + case Iop_Scale2_64Fx2: + TERNARY(ity_RMode,Ity_V128,Ity_V128, Ity_V128); + case Iop_Log2_32Fx4: + case Iop_Log2_64Fx2: + UNARY(Ity_V128, Ity_V128); + case Iop_V128to64: case Iop_V128HIto64: case Iop_NarrowUn16to8x8: case Iop_NarrowUn32to16x4: @@ -3076,6 +3097,9 @@ void typeOfPrimop ( IROp op, case Iop_InterleaveOddLanes8x16: case Iop_InterleaveEvenLanes8x16: case Iop_InterleaveOddLanes16x8: case Iop_InterleaveEvenLanes16x8: case Iop_InterleaveOddLanes32x4: case Iop_InterleaveEvenLanes32x4: + case Iop_PackOddLanes8x16: case Iop_PackEvenLanes8x16: + case Iop_PackOddLanes16x8: case Iop_PackEvenLanes16x8: + case Iop_PackOddLanes32x4: case Iop_PackEvenLanes32x4: case Iop_Perm8x16: case Iop_Perm32x4: case Iop_RecipStep32Fx4: case Iop_RecipStep64Fx2: case Iop_RSqrtStep32Fx4: case Iop_RSqrtStep64Fx2: @@ -3243,6 +3267,7 @@ void typeOfPrimop ( IROp op, case Iop_Mul64Fx2: case Iop_Div64Fx2: case Iop_Add32Fx4: case Iop_Sub32Fx4: case Iop_Mul32Fx4: case Iop_Div32Fx4: + case Iop_F64x2_2toQ32x4: case Iop_F32x4_2toQ16x8: TERNARY(ity_RMode,Ity_V128,Ity_V128, Ity_V128); case Iop_Add64Fx4: case Iop_Sub64Fx4: diff --git a/VEX/pub/libvex_ir.h b/VEX/pub/libvex_ir.h index 57fa9b6b20..5cc37e7df8 100644 --- a/VEX/pub/libvex_ir.h +++ b/VEX/pub/libvex_ir.h @@ -1351,6 +1351,13 @@ typedef square root of each element in the operand vector. */ Iop_RSqrtEst32Fx4, + /* Scaling of vector with a power of 2 (wd[i] <- ws[i] * 2^wt[i]) */ + Iop_Scale2_32Fx4, + + /* Vector floating-point base 2 logarithm */ + Iop_Log2_32Fx4, + + /* Vector Reciprocal Square Root Step computes (3.0 - arg1 * arg2) / 2.0. Note, that of one of the arguments is zero and another one is infiinty of arbitrary sign the result of the operation is 1.5. */ @@ -1375,9 +1382,16 @@ typedef /* FIXME: what kind of rounding in F32x4 -> F16x4 case? */ Iop_F32toF16x4, Iop_F16toF32x4, /* F32x4 <-> F16x4 */ + + /* -- Double to/from half conversion -- */ Iop_F64toF16x2, Iop_F16toF64x2, + /* Values from two registers converted in smaller type and put in one + IRRoundingMode(I32) x (F32x4 | F32x4) -> Q16x8 */ + Iop_F32x4_2toQ16x8, + + /* --- 32x4 lowest-lane-only scalar FP --- */ /* In binary cases, upper 3/4 is copied from first operand. In @@ -1407,12 +1421,23 @@ typedef /* binary :: IRRoundingMode(I32) x V128 -> V128 */ Iop_Sqrt64Fx2, + /* Scaling of vector with a power of 2 (wd[i] <- ws[i] * 2^wt[i]) */ + Iop_Scale2_64Fx2, + + /* Vector floating-point base 2 logarithm */ + Iop_Log2_64Fx2, + /* see 32Fx4 variants for description */ Iop_RecipEst64Fx2, // unary Iop_RecipStep64Fx2, // binary Iop_RSqrtEst64Fx2, // unary Iop_RSqrtStep64Fx2, // binary + + /* Values from two registers converted in smaller type and put in one + IRRoundingMode(I32) x (F64x2 | F64x2) -> Q32x4 */ + Iop_F64x2_2toQ32x4, + /* --- 64x2 lowest-lane-only scalar FP --- */ /* In binary cases, upper half is copied from first operand. In @@ -1761,6 +1786,11 @@ typedef Iop_InterleaveOddLanes16x8, Iop_InterleaveEvenLanes16x8, Iop_InterleaveOddLanes32x4, Iop_InterleaveEvenLanes32x4, + /* Pack even/odd lanes. */ + Iop_PackOddLanes8x16, Iop_PackEvenLanes8x16, + Iop_PackOddLanes16x8, Iop_PackEvenLanes16x8, + Iop_PackOddLanes32x4, Iop_PackEvenLanes32x4, + /* CONCATENATION -- build a new value by concatenating either the even or odd lanes of both operands. Note that Cat{Odd,Even}Lanes64x2 are identical to Interleave{HI,LO}64x2 diff --git a/memcheck/mc_translate.c b/memcheck/mc_translate.c index 44b6a73136..9d4f651a58 100644 --- a/memcheck/mc_translate.c +++ b/memcheck/mc_translate.c @@ -2996,12 +2996,14 @@ IRAtom* expr2vbits_Triop ( MCEnv* mce, case Iop_Sub64Fx2: case Iop_Mul64Fx2: case Iop_Div64Fx2: + case Iop_Scale2_64Fx2: return binary64Fx2_w_rm(mce, vatom1, vatom2, vatom3); case Iop_Add32Fx4: case Iop_Sub32Fx4: case Iop_Mul32Fx4: case Iop_Div32Fx4: + case Iop_Scale2_32Fx4: return binary32Fx4_w_rm(mce, vatom1, vatom2, vatom3); case Iop_Add64Fx4: @@ -3016,6 +3018,18 @@ IRAtom* expr2vbits_Triop ( MCEnv* mce, case Iop_Div32Fx8: return binary32Fx8_w_rm(mce, vatom1, vatom2, vatom3); + case Iop_F32x4_2toQ16x8: + return assignNew('V', mce, Ity_V128, + binop(Iop_PackEvenLanes16x8, + unary32Fx4_w_rm(mce, vatom1, vatom2), + unary32Fx4_w_rm(mce, vatom1, vatom3))); + case Iop_F64x2_2toQ32x4: + return assignNew('V', mce, Ity_V128, + binop(Iop_PackEvenLanes32x4, + unary64Fx2_w_rm(mce, vatom1, vatom2), + unary64Fx2_w_rm(mce, vatom1, vatom3))); + + default: ppIROp(op); VG_(tool_panic)("memcheck:expr2vbits_Triop"); @@ -3737,6 +3751,12 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce, case Iop_InterleaveEvenLanes8x16: case Iop_InterleaveEvenLanes16x8: case Iop_InterleaveEvenLanes32x4: + case Iop_PackOddLanes8x16: + case Iop_PackOddLanes16x8: + case Iop_PackOddLanes32x4: + case Iop_PackEvenLanes8x16: + case Iop_PackEvenLanes16x8: + case Iop_PackEvenLanes32x4: return assignNew('V', mce, Ity_V128, binop(op, vatom1, vatom2)); case Iop_GetElem8x16: @@ -4432,6 +4452,7 @@ IRExpr* expr2vbits_Unop ( MCEnv* mce, IROp op, IRAtom* atom ) case Iop_Neg64Fx2: case Iop_RSqrtEst64Fx2: case Iop_RecipEst64Fx2: + case Iop_Log2_64Fx2: return unary64Fx2(mce, vatom); case Iop_Sqrt64F0x2: @@ -4458,6 +4479,7 @@ IRExpr* expr2vbits_Unop ( MCEnv* mce, IROp op, IRAtom* atom ) case Iop_Abs32Fx4: case Iop_Neg32Fx4: case Iop_RSqrtEst32Fx4: + case Iop_Log2_32Fx4: return unary32Fx4(mce, vatom); case Iop_I32UtoFx2: diff --git a/memcheck/tests/vbit-test/irops.c b/memcheck/tests/vbit-test/irops.c index 7f9ce90b03..242184b4d5 100644 --- a/memcheck/tests/vbit-test/irops.c +++ b/memcheck/tests/vbit-test/irops.c @@ -623,6 +623,8 @@ static irop_t irops[] = { { DEFOP(Iop_PwMin32Fx4, UNDEF_UNKNOWN), }, { DEFOP(Iop_Abs32Fx4, UNDEF_UNKNOWN), }, { DEFOP(Iop_Sqrt32Fx4, UNDEF_UNKNOWN), }, + { DEFOP(Iop_Scale2_32Fx4, UNDEF_UNKNOWN), }, + { DEFOP(Iop_Log2_32Fx4, UNDEF_UNKNOWN), }, { DEFOP(Iop_Neg32Fx4, UNDEF_UNKNOWN), }, { DEFOP(Iop_RecipEst32Fx4, UNDEF_UNKNOWN), }, { DEFOP(Iop_RecipStep32Fx4, UNDEF_UNKNOWN), }, @@ -646,6 +648,8 @@ static irop_t irops[] = { { DEFOP(Iop_F16toF32x4, UNDEF_UNKNOWN), }, { DEFOP(Iop_F64toF16x2, UNDEF_UNKNOWN), }, { DEFOP(Iop_F16toF64x2, UNDEF_UNKNOWN), }, + { DEFOP(Iop_F32x4_2toQ16x8, UNDEF_UNKNOWN), }, + { DEFOP(Iop_F64x2_2toQ32x4, UNDEF_UNKNOWN), }, { DEFOP(Iop_Add32F0x4, UNDEF_UNKNOWN), }, { DEFOP(Iop_Sub32F0x4, UNDEF_UNKNOWN), }, { DEFOP(Iop_Mul32F0x4, UNDEF_UNKNOWN), }, @@ -671,6 +675,8 @@ static irop_t irops[] = { { DEFOP(Iop_CmpUN64Fx2, UNDEF_UNKNOWN), }, { DEFOP(Iop_Abs64Fx2, UNDEF_UNKNOWN), }, { DEFOP(Iop_Sqrt64Fx2, UNDEF_UNKNOWN), }, + { DEFOP(Iop_Scale2_64Fx2, UNDEF_UNKNOWN), }, + { DEFOP(Iop_Log2_64Fx2, UNDEF_UNKNOWN), }, { DEFOP(Iop_Neg64Fx2, UNDEF_UNKNOWN), }, { DEFOP(Iop_RecipEst64Fx2, UNDEF_UNKNOWN), }, { DEFOP(Iop_RecipStep64Fx2, UNDEF_UNKNOWN), }, @@ -979,6 +985,12 @@ static irop_t irops[] = { { DEFOP(Iop_InterleaveEvenLanes16x8, UNDEF_UNKNOWN), }, { DEFOP(Iop_InterleaveOddLanes32x4, UNDEF_UNKNOWN), }, { DEFOP(Iop_InterleaveEvenLanes32x4, UNDEF_UNKNOWN), }, + { DEFOP(Iop_PackOddLanes8x16, UNDEF_UNKNOWN), }, + { DEFOP(Iop_PackEvenLanes8x16, UNDEF_UNKNOWN), }, + { DEFOP(Iop_PackOddLanes16x8, UNDEF_UNKNOWN), }, + { DEFOP(Iop_PackEvenLanes16x8, UNDEF_UNKNOWN), }, + { DEFOP(Iop_PackOddLanes32x4, UNDEF_UNKNOWN), }, + { DEFOP(Iop_PackEvenLanes32x4, UNDEF_UNKNOWN), }, { DEFOP(Iop_CatOddLanes8x16, UNDEF_UNKNOWN), }, { DEFOP(Iop_CatOddLanes16x8, UNDEF_UNKNOWN), }, { DEFOP(Iop_CatOddLanes32x4, UNDEF_UNKNOWN), },