From: Álvaro Fernández Rojas Date: Thu, 22 May 2025 08:39:47 +0000 (+0200) Subject: generic: backport upstream v6.16 r8169 patches X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=91ce7f606a623edab99d1928480c65fc44ee8665;p=thirdparty%2Fopenwrt.git generic: backport upstream v6.16 r8169 patches f24f7b2f3af9 r8169: add support for RTL8127A 4f51e7d370a0 r8169: merge chip versions 52 and 53 (RTL8117) f372ef6ed5a6 r8169: merge chip versions 64 and 65 (RTL8125D) 4dec0702b862 r8169: merge chip versions 70 and 71 (RTL8126A) b7ed5d5a78fc r8169: use pci_prepare_to_sleep in rtl_shutdown fe733618b27a r8169: add RTL_GIGA_MAC_VER_LAST to facilitate adding support for new chip versions 2b065c098c37 r8169: refactor chip version detection 0c49baf099ba r8169: add helper rtl8125_phy_param 8c40d99e5f43 r8169: add helper rtl_csi_mod for accessing extended config space Signed-off-by: Álvaro Fernández Rojas --- diff --git a/target/linux/generic/backport-6.12/780-34-v6.16-r8169-add-helper-rtl_csi_mod-for-accessing-extended.patch b/target/linux/generic/backport-6.12/780-34-v6.16-r8169-add-helper-rtl_csi_mod-for-accessing-extended.patch new file mode 100644 index 00000000000..a24485d1d6d --- /dev/null +++ b/target/linux/generic/backport-6.12/780-34-v6.16-r8169-add-helper-rtl_csi_mod-for-accessing-extended.patch @@ -0,0 +1,74 @@ +From 8c40d99e5f43e0545a3f4fea9156313847e2eb79 Mon Sep 17 00:00:00 2001 +From: Heiner Kallweit +Date: Wed, 9 Apr 2025 21:05:37 +0200 +Subject: [PATCH] r8169: add helper rtl_csi_mod for accessing extended config + space + +Add a helper for the Realtek-specific mechanism for accessing extended +config space if native access isn't possible. +This avoids code duplication. + +Signed-off-by: Heiner Kallweit +Link: https://patch.msgid.link/b368fd91-57d7-4cb5-9342-98b4d8fe9aea@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/realtek/r8169_main.c | 26 ++++++++++++++--------- + 1 file changed, 16 insertions(+), 10 deletions(-) + +--- a/drivers/net/ethernet/realtek/r8169_main.c ++++ b/drivers/net/ethernet/realtek/r8169_main.c +@@ -2852,10 +2852,23 @@ static u32 rtl_csi_read(struct rtl8169_p + RTL_R32(tp, CSIDR) : ~0; + } + ++static void rtl_csi_mod(struct rtl8169_private *tp, int addr, ++ u32 mask, u32 set) ++{ ++ u32 val; ++ ++ WARN(addr % 4, "Invalid CSI address %#x\n", addr); ++ ++ netdev_notice_once(tp->dev, ++ "No native access to PCI extended config space, falling back to CSI\n"); ++ ++ val = rtl_csi_read(tp, addr); ++ rtl_csi_write(tp, addr, (val & ~mask) | set); ++} ++ + static void rtl_disable_zrxdc_timeout(struct rtl8169_private *tp) + { + struct pci_dev *pdev = tp->pci_dev; +- u32 csi; + int rc; + u8 val; + +@@ -2872,16 +2885,12 @@ static void rtl_disable_zrxdc_timeout(st + } + } + +- netdev_notice_once(tp->dev, +- "No native access to PCI extended config space, falling back to CSI\n"); +- csi = rtl_csi_read(tp, RTL_GEN3_RELATED_OFF); +- rtl_csi_write(tp, RTL_GEN3_RELATED_OFF, csi & ~RTL_GEN3_ZRXDC_NONCOMPL); ++ rtl_csi_mod(tp, RTL_GEN3_RELATED_OFF, RTL_GEN3_ZRXDC_NONCOMPL, 0); + } + + static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val) + { + struct pci_dev *pdev = tp->pci_dev; +- u32 csi; + + /* According to Realtek the value at config space address 0x070f + * controls the L0s/L1 entrance latency. We try standard ECAM access +@@ -2893,10 +2902,7 @@ static void rtl_set_aspm_entry_latency(s + pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) + return; + +- netdev_notice_once(tp->dev, +- "No native access to PCI extended config space, falling back to CSI\n"); +- csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; +- rtl_csi_write(tp, 0x070c, csi | val << 24); ++ rtl_csi_mod(tp, 0x070c, 0xff000000, val << 24); + } + + static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) diff --git a/target/linux/generic/backport-6.12/780-35-v6.16-r8169-add-helper-rtl8125_phy_param.patch b/target/linux/generic/backport-6.12/780-35-v6.16-r8169-add-helper-rtl8125_phy_param.patch new file mode 100644 index 00000000000..30ebb4b6f48 --- /dev/null +++ b/target/linux/generic/backport-6.12/780-35-v6.16-r8169-add-helper-rtl8125_phy_param.patch @@ -0,0 +1,82 @@ +From 0c49baf099ba2147a6ff3bbdc3197c6ddbee5469 Mon Sep 17 00:00:00 2001 +From: Heiner Kallweit +Date: Wed, 9 Apr 2025 21:14:47 +0200 +Subject: [PATCH] r8169: add helper rtl8125_phy_param + +The integrated PHY's of RTL8125/8126 have an own mechanism to access +PHY parameters, similar to what r8168g_phy_param does on earlier PHY +versions. Add helper rtl8125_phy_param to simplify the code. + +Signed-off-by: Heiner Kallweit +Link: https://patch.msgid.link/847b7356-12d6-441b-ade9-4b6e1539b84a@gmail.com +Signed-off-by: Jakub Kicinski +--- + .../net/ethernet/realtek/r8169_phy_config.c | 36 +++++++++---------- + 1 file changed, 16 insertions(+), 20 deletions(-) + +--- a/drivers/net/ethernet/realtek/r8169_phy_config.c ++++ b/drivers/net/ethernet/realtek/r8169_phy_config.c +@@ -50,6 +50,15 @@ static void r8168g_phy_param(struct phy_ + phy_restore_page(phydev, oldpage, 0); + } + ++static void rtl8125_phy_param(struct phy_device *phydev, u16 parm, ++ u16 mask, u16 val) ++{ ++ phy_lock_mdio_bus(phydev); ++ __phy_write_mmd(phydev, MDIO_MMD_VEND2, 0xb87c, parm); ++ __phy_modify_mmd(phydev, MDIO_MMD_VEND2, 0xb87e, mask, val); ++ phy_unlock_mdio_bus(phydev); ++} ++ + struct phy_reg { + u16 reg; + u16 val; +@@ -1004,12 +1013,8 @@ static void rtl8125a_2_hw_phy_config(str + phy_write_paged(phydev, 0xac5, 0x16, 0x01ff); + phy_modify_paged(phydev, 0xac8, 0x15, 0x00f0, 0x0030); + +- phy_write(phydev, 0x1f, 0x0b87); +- phy_write(phydev, 0x16, 0x80a2); +- phy_write(phydev, 0x17, 0x0153); +- phy_write(phydev, 0x16, 0x809c); +- phy_write(phydev, 0x17, 0x0153); +- phy_write(phydev, 0x1f, 0x0000); ++ rtl8125_phy_param(phydev, 0x80a2, 0xffff, 0x0153); ++ rtl8125_phy_param(phydev, 0x809c, 0xffff, 0x0153); + + phy_write(phydev, 0x1f, 0x0a43); + phy_write(phydev, 0x13, 0x81B3); +@@ -1061,14 +1066,9 @@ static void rtl8125b_hw_phy_config(struc + phy_modify_paged(phydev, 0xac4, 0x13, 0x00f0, 0x0090); + phy_modify_paged(phydev, 0xad3, 0x10, 0x0003, 0x0001); + +- phy_write(phydev, 0x1f, 0x0b87); +- phy_write(phydev, 0x16, 0x80f5); +- phy_write(phydev, 0x17, 0x760e); +- phy_write(phydev, 0x16, 0x8107); +- phy_write(phydev, 0x17, 0x360e); +- phy_write(phydev, 0x16, 0x8551); +- phy_modify(phydev, 0x17, 0xff00, 0x0800); +- phy_write(phydev, 0x1f, 0x0000); ++ rtl8125_phy_param(phydev, 0x80f5, 0xffff, 0x760e); ++ rtl8125_phy_param(phydev, 0x8107, 0xffff, 0x360e); ++ rtl8125_phy_param(phydev, 0x8551, 0xff00, 0x0800); + + phy_modify_paged(phydev, 0xbf0, 0x10, 0xe000, 0xa000); + phy_modify_paged(phydev, 0xbf4, 0x13, 0x0f00, 0x0300); +@@ -1110,12 +1110,8 @@ static void rtl8125bp_hw_phy_config(stru + + r8168g_phy_param(phydev, 0x8010, 0x0800, 0x0000); + +- phy_write(phydev, 0x1f, 0x0b87); +- phy_write(phydev, 0x16, 0x8088); +- phy_modify(phydev, 0x17, 0xff00, 0x9000); +- phy_write(phydev, 0x16, 0x808f); +- phy_modify(phydev, 0x17, 0xff00, 0x9000); +- phy_write(phydev, 0x1f, 0x0000); ++ rtl8125_phy_param(phydev, 0x8088, 0xff00, 0x9000); ++ rtl8125_phy_param(phydev, 0x808f, 0xff00, 0x9000); + + r8168g_phy_param(phydev, 0x8174, 0x2000, 0x1800); + diff --git a/target/linux/generic/backport-6.12/780-36-v6.16-r8169-refactor-chip-version-detection.patch b/target/linux/generic/backport-6.12/780-36-v6.16-r8169-refactor-chip-version-detection.patch new file mode 100644 index 00000000000..e0682bea867 --- /dev/null +++ b/target/linux/generic/backport-6.12/780-36-v6.16-r8169-refactor-chip-version-detection.patch @@ -0,0 +1,401 @@ +From 2b065c098c37a3ed28df7c3be59dca61b9da8402 Mon Sep 17 00:00:00 2001 +From: Heiner Kallweit +Date: Tue, 15 Apr 2025 21:29:34 +0200 +Subject: [PATCH] r8169: refactor chip version detection + +Refactor chip version detection and merge both configuration tables. +Apart from reducing the code by a third, this paves the way for +merging chip version handling if only difference is the firmware. + +Signed-off-by: Heiner Kallweit +Reviewed-by: Michal Swiatkowski +Link: https://patch.msgid.link/1fea533a-dd5a-4198-a9e2-895e11083947@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/realtek/r8169_main.c | 325 +++++++++------------- + 1 file changed, 128 insertions(+), 197 deletions(-) + +--- a/drivers/net/ethernet/realtek/r8169_main.c ++++ b/drivers/net/ethernet/realtek/r8169_main.c +@@ -91,61 +91,114 @@ + #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) + #define JUMBO_16K (SZ_16K - VLAN_ETH_HLEN - ETH_FCS_LEN) + +-static const struct { ++static const struct rtl_chip_info { ++ u16 mask; ++ u16 val; ++ enum mac_version mac_version; + const char *name; + const char *fw_name; + } rtl_chip_infos[] = { +- /* PCI devices. */ +- [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, +- [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, +- [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, +- [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, +- [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, +- /* PCI-E devices. */ +- [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, +- [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, +- [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, +- [RTL_GIGA_MAC_VER_10] = {"RTL8101e/RTL8100e" }, +- [RTL_GIGA_MAC_VER_14] = {"RTL8401" }, +- [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, +- [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, +- [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, +- [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, +- [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, +- [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, +- [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, +- [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, +- [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, +- [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, +- [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, +- [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, +- [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, +- [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, +- [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, +- [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, +- [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, +- [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, +- [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, +- [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, +- [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, +- [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, +- [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, +- [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, +- [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, +- [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, +- [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, +- [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, +- [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, +- [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3}, +- [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117", }, +- [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3}, +- /* reserve 62 for CFG_METHOD_4 in the vendor driver */ +- [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2}, +- [RTL_GIGA_MAC_VER_64] = {"RTL8125D", FIRMWARE_8125D_1}, +- [RTL_GIGA_MAC_VER_65] = {"RTL8125D", FIRMWARE_8125D_2}, +- [RTL_GIGA_MAC_VER_66] = {"RTL8125BP", FIRMWARE_8125BP_2}, +- [RTL_GIGA_MAC_VER_70] = {"RTL8126A", FIRMWARE_8126A_2}, +- [RTL_GIGA_MAC_VER_71] = {"RTL8126A", FIRMWARE_8126A_3}, ++ /* 8126A family. */ ++ { 0x7cf, 0x64a, RTL_GIGA_MAC_VER_71, "RTL8126A", FIRMWARE_8126A_3 }, ++ { 0x7cf, 0x649, RTL_GIGA_MAC_VER_70, "RTL8126A", FIRMWARE_8126A_2 }, ++ ++ /* 8125BP family. */ ++ { 0x7cf, 0x681, RTL_GIGA_MAC_VER_66, "RTL8125BP", FIRMWARE_8125BP_2 }, ++ ++ /* 8125D family. */ ++ { 0x7cf, 0x689, RTL_GIGA_MAC_VER_65, "RTL8125D", FIRMWARE_8125D_2 }, ++ { 0x7cf, 0x688, RTL_GIGA_MAC_VER_64, "RTL8125D", FIRMWARE_8125D_1 }, ++ ++ /* 8125B family. */ ++ { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63, "RTL8125B", FIRMWARE_8125B_2 }, ++ ++ /* 8125A family. */ ++ { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61, "RTL8125A", FIRMWARE_8125A_3 }, ++ ++ /* RTL8117 */ ++ { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53, "RTL8168fp/RTL8117" }, ++ { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52, "RTL8168fp/RTL8117", ++ FIRMWARE_8168FP_3 }, ++ ++ /* 8168EP family. */ ++ { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51, "RTL8168ep/8111ep" }, ++ ++ /* 8168H family. */ ++ { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46, "RTL8168h/8111h", ++ FIRMWARE_8168H_2 }, ++ /* Realtek calls it RTL8168M, but it's handled like RTL8168H */ ++ { 0x7cf, 0x6c0, RTL_GIGA_MAC_VER_46, "RTL8168M", FIRMWARE_8168H_2 }, ++ ++ /* 8168G family. */ ++ { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44, "RTL8411b", FIRMWARE_8411_2 }, ++ { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42, "RTL8168gu/8111gu", ++ FIRMWARE_8168G_3 }, ++ { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40, "RTL8168g/8111g", ++ FIRMWARE_8168G_2 }, ++ ++ /* 8168F family. */ ++ { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38, "RTL8411", FIRMWARE_8411_1 }, ++ { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36, "RTL8168f/8111f", ++ FIRMWARE_8168F_2 }, ++ { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35, "RTL8168f/8111f", ++ FIRMWARE_8168F_1 }, ++ ++ /* 8168E family. */ ++ { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34, "RTL8168evl/8111evl", ++ FIRMWARE_8168E_3 }, ++ { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32, "RTL8168e/8111e", ++ FIRMWARE_8168E_1 }, ++ { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33, "RTL8168e/8111e", ++ FIRMWARE_8168E_2 }, ++ ++ /* 8168D family. */ ++ { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25, "RTL8168d/8111d", ++ FIRMWARE_8168D_1 }, ++ { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26, "RTL8168d/8111d", ++ FIRMWARE_8168D_2 }, ++ ++ /* 8168DP family. */ ++ { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28, "RTL8168dp/8111dp" }, ++ { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31, "RTL8168dp/8111dp" }, ++ ++ /* 8168C family. */ ++ { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23, "RTL8168cp/8111cp" }, ++ { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18, "RTL8168cp/8111cp" }, ++ { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24, "RTL8168cp/8111cp" }, ++ { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19, "RTL8168c/8111c" }, ++ { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20, "RTL8168c/8111c" }, ++ { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21, "RTL8168c/8111c" }, ++ { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22, "RTL8168c/8111c" }, ++ ++ /* 8168B family. */ ++ { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17, "RTL8168b/8111b" }, ++ /* This one is very old and rare, support has been removed. ++ * { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11, "RTL8168b/8111b" }, ++ */ ++ ++ /* 8101 family. */ ++ { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39, "RTL8106e", FIRMWARE_8106E_1 }, ++ { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37, "RTL8402", FIRMWARE_8402_1 }, ++ { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29, "RTL8105e", FIRMWARE_8105E_1 }, ++ { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30, "RTL8105e", FIRMWARE_8105E_1 }, ++ { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08, "RTL8102e" }, ++ { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08, "RTL8102e" }, ++ { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07, "RTL8102e" }, ++ { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07, "RTL8102e" }, ++ { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14, "RTL8401" }, ++ { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09, "RTL8102e/RTL8103e" }, ++ { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09, "RTL8102e/RTL8103e" }, ++ { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10, "RTL8101e/RTL8100e" }, ++ ++ /* 8110 family. */ ++ { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06, "RTL8169sc/8110sc" }, ++ { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05, "RTL8169sc/8110sc" }, ++ { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04, "RTL8169sb/8110sb" }, ++ { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03, "RTL8110s" }, ++ { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02, "RTL8169s" }, ++ ++ /* Catch-all */ ++ { 0x000, 0x000, RTL_GIGA_MAC_NONE } + }; + + static const struct pci_device_id rtl8169_pci_tbl[] = { +@@ -2265,151 +2318,30 @@ static const struct ethtool_ops rtl8169_ + .get_eth_ctrl_stats = rtl8169_get_eth_ctrl_stats, + }; + +-static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii) ++static const struct rtl_chip_info *rtl8169_get_chip_version(u16 xid, bool gmii) + { +- /* +- * The driver currently handles the 8168Bf and the 8168Be identically +- * but they can be identified more specifically through the test below +- * if needed: +- * +- * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be +- * +- * Same thing for the 8101Eb and the 8101Ec: +- * +- * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec +- */ +- static const struct rtl_mac_info { +- u16 mask; +- u16 val; +- enum mac_version ver; +- } mac_info[] = { +- /* 8126A family. */ +- { 0x7cf, 0x64a, RTL_GIGA_MAC_VER_71 }, +- { 0x7cf, 0x649, RTL_GIGA_MAC_VER_70 }, +- +- /* 8125BP family. */ +- { 0x7cf, 0x681, RTL_GIGA_MAC_VER_66 }, +- +- /* 8125D family. */ +- { 0x7cf, 0x689, RTL_GIGA_MAC_VER_65 }, +- { 0x7cf, 0x688, RTL_GIGA_MAC_VER_64 }, +- +- /* 8125B family. */ +- { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 }, +- +- /* 8125A family. */ +- { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61 }, +- /* It seems only XID 609 made it to the mass market. +- * { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, +- * { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, +- */ +- +- /* RTL8117 */ +- { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 }, +- { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, +- +- /* 8168EP family. */ +- { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, +- /* It seems this chip version never made it to +- * the wild. Let's disable detection. +- * { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, +- * { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, +- */ +- +- /* 8168H family. */ +- { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, +- /* It seems this chip version never made it to +- * the wild. Let's disable detection. +- * { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, +- */ +- /* Realtek calls it RTL8168M, but it's handled like RTL8168H */ +- { 0x7cf, 0x6c0, RTL_GIGA_MAC_VER_46 }, +- +- /* 8168G family. */ +- { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, +- { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, +- /* It seems this chip version never made it to +- * the wild. Let's disable detection. +- * { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, +- */ +- { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, +- +- /* 8168F family. */ +- { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, +- { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, +- { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, +- +- /* 8168E family. */ +- { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, +- { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, +- { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, +- +- /* 8168D family. */ +- { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, +- { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, +- +- /* 8168DP family. */ +- /* It seems this early RTL8168dp version never made it to +- * the wild. Support has been removed. +- * { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, +- */ +- { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, +- { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, +- +- /* 8168C family. */ +- { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, +- { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, +- { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, +- { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, +- { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, +- { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, +- { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, +- +- /* 8168B family. */ +- { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, +- /* This one is very old and rare, support has been removed. +- * { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, +- */ +- +- /* 8101 family. */ +- { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, +- { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, +- { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, +- { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, +- { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, +- { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, +- { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, +- { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, +- { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 }, +- { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, +- { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, +- { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10 }, +- +- /* 8110 family. */ +- { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, +- { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, +- { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, +- { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, +- { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, +- +- /* Catch-all */ +- { 0x000, 0x000, RTL_GIGA_MAC_NONE } ++ /* Chips combining a 1Gbps MAC with a 100Mbps PHY */ ++ static const struct rtl_chip_info rtl8106eus_info = { ++ .mac_version = RTL_GIGA_MAC_VER_43, ++ .name = "RTL8106eus", ++ .fw_name = FIRMWARE_8106E_2, + }; +- const struct rtl_mac_info *p = mac_info; +- enum mac_version ver; ++ static const struct rtl_chip_info rtl8107e_info = { ++ .mac_version = RTL_GIGA_MAC_VER_48, ++ .name = "RTL8107e", ++ .fw_name = FIRMWARE_8107E_2, ++ }; ++ const struct rtl_chip_info *p = rtl_chip_infos; + + while ((xid & p->mask) != p->val) + p++; +- ver = p->ver; + +- if (ver != RTL_GIGA_MAC_NONE && !gmii) { +- if (ver == RTL_GIGA_MAC_VER_42) +- ver = RTL_GIGA_MAC_VER_43; +- else if (ver == RTL_GIGA_MAC_VER_46) +- ver = RTL_GIGA_MAC_VER_48; +- } ++ if (p->mac_version == RTL_GIGA_MAC_VER_42 && !gmii) ++ return &rtl8106eus_info; ++ if (p->mac_version == RTL_GIGA_MAC_VER_46 && !gmii) ++ return &rtl8107e_info; + +- return ver; ++ return p; + } + + static void rtl_release_firmware(struct rtl8169_private *tp) +@@ -5439,9 +5371,9 @@ static bool rtl_aspm_is_safe(struct rtl8 + + static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) + { ++ const struct rtl_chip_info *chip; + struct rtl8169_private *tp; + int jumbo_max, region, rc; +- enum mac_version chipset; + struct net_device *dev; + u32 txconfig; + u16 xid; +@@ -5491,12 +5423,13 @@ static int rtl_init_one(struct pci_dev * + xid = (txconfig >> 20) & 0xfcf; + + /* Identify chip attached to board */ +- chipset = rtl8169_get_mac_version(xid, tp->supports_gmii); +- if (chipset == RTL_GIGA_MAC_NONE) ++ chip = rtl8169_get_chip_version(xid, tp->supports_gmii); ++ if (chip->mac_version == RTL_GIGA_MAC_NONE) + return dev_err_probe(&pdev->dev, -ENODEV, + "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n", + xid); +- tp->mac_version = chipset; ++ tp->mac_version = chip->mac_version; ++ tp->fw_name = chip->fw_name; + + /* Disable ASPM L1 as that cause random device stop working + * problems as well as full system hangs for some PCIe devices users. +@@ -5601,8 +5534,6 @@ static int rtl_init_one(struct pci_dev * + + rtl_set_irq_mask(tp); + +- tp->fw_name = rtl_chip_infos[chipset].fw_name; +- + tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), + &tp->counters_phys_addr, + GFP_KERNEL); +@@ -5627,7 +5558,7 @@ static int rtl_init_one(struct pci_dev * + } + + netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n", +- rtl_chip_infos[chipset].name, dev->dev_addr, xid, tp->irq); ++ chip->name, dev->dev_addr, xid, tp->irq); + + if (jumbo_max) + netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n", diff --git a/target/linux/generic/backport-6.12/780-37-v6.16-r8169-add-RTL_GIGA_MAC_VER_LAST-to-facilitate-adding.patch b/target/linux/generic/backport-6.12/780-37-v6.16-r8169-add-RTL_GIGA_MAC_VER_LAST-to-facilitate-adding.patch new file mode 100644 index 00000000000..8948a296ca4 --- /dev/null +++ b/target/linux/generic/backport-6.12/780-37-v6.16-r8169-add-RTL_GIGA_MAC_VER_LAST-to-facilitate-adding.patch @@ -0,0 +1,159 @@ +From fe733618b27a8c033f0d246c2efff56fca322656 Mon Sep 17 00:00:00 2001 +From: Heiner Kallweit +Date: Tue, 15 Apr 2025 21:39:23 +0200 +Subject: [PATCH] r8169: add RTL_GIGA_MAC_VER_LAST to facilitate adding support + for new chip versions + +Add a new mac_version enum value RTL_GIGA_MAC_VER_LAST. Benefit is that +when adding support for a new chip version we have to touch less code, +except something changes fundamentally. + +Signed-off-by: Heiner Kallweit +Reviewed-by: Simon Horman +Link: https://patch.msgid.link/06991f47-2aec-4aa2-8918-2c6e79332303@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/realtek/r8169.h | 3 ++- + drivers/net/ethernet/realtek/r8169_main.c | 28 +++++++++++------------ + 2 files changed, 16 insertions(+), 15 deletions(-) + +--- a/drivers/net/ethernet/realtek/r8169.h ++++ b/drivers/net/ethernet/realtek/r8169.h +@@ -73,7 +73,8 @@ enum mac_version { + RTL_GIGA_MAC_VER_66, + RTL_GIGA_MAC_VER_70, + RTL_GIGA_MAC_VER_71, +- RTL_GIGA_MAC_NONE ++ RTL_GIGA_MAC_NONE, ++ RTL_GIGA_MAC_VER_LAST = RTL_GIGA_MAC_NONE - 1 + }; + + struct rtl8169_private; +--- a/drivers/net/ethernet/realtek/r8169_main.c ++++ b/drivers/net/ethernet/realtek/r8169_main.c +@@ -1289,7 +1289,7 @@ static void rtl_writephy(struct rtl8169_ + case RTL_GIGA_MAC_VER_31: + r8168dp_2_mdio_write(tp, location, val); + break; +- case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_71: ++ case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST: + r8168g_mdio_write(tp, location, val); + break; + default: +@@ -1304,7 +1304,7 @@ static int rtl_readphy(struct rtl8169_pr + case RTL_GIGA_MAC_VER_28: + case RTL_GIGA_MAC_VER_31: + return r8168dp_2_mdio_read(tp, location); +- case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_71: ++ case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST: + return r8168g_mdio_read(tp, location); + default: + return r8169_mdio_read(tp, location); +@@ -1656,7 +1656,7 @@ static void __rtl8169_set_wol(struct rtl + break; + case RTL_GIGA_MAC_VER_34: + case RTL_GIGA_MAC_VER_37: +- case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_71: ++ case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_LAST: + r8169_mod_reg8_cond(tp, Config2, PME_SIGNAL, wolopts); + break; + default: +@@ -2129,7 +2129,7 @@ static void rtl_set_eee_txidle_timer(str + tp->tx_lpi_timer = timer_val; + r8168_mac_ocp_write(tp, 0xe048, timer_val); + break; +- case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_71: ++ case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: + tp->tx_lpi_timer = timer_val; + RTL_W16(tp, EEE_TXIDLE_TIMER_8125, timer_val); + break; +@@ -2491,7 +2491,7 @@ static void rtl_init_rxcfg(struct rtl816 + case RTL_GIGA_MAC_VER_61: + RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); + break; +- case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_71: ++ case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_LAST: + RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST | + RX_PAUSE_SLOT_ON); + break; +@@ -2623,7 +2623,7 @@ static void rtl_wait_txrx_fifo_empty(str + case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61: + rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); + break; +- case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_71: ++ case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_LAST: + RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); + rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); + rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42); +@@ -2898,7 +2898,7 @@ static void rtl_enable_exit_l1(struct rt + case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38: + rtl_eri_set_bits(tp, 0xd4, 0x0c00); + break; +- case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_71: ++ case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST: + r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80); + break; + default: +@@ -2912,7 +2912,7 @@ static void rtl_disable_exit_l1(struct r + case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: + rtl_eri_clear_bits(tp, 0xd4, 0x1f00); + break; +- case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_71: ++ case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST: + r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0); + break; + default: +@@ -2950,7 +2950,7 @@ static void rtl_hw_aspm_clkreq_enable(st + + switch (tp->mac_version) { + case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: +- case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_71: ++ case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: + /* reset ephy tx/rx disable timer */ + r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0); + /* chip can trigger L1.2 */ +@@ -2962,7 +2962,7 @@ static void rtl_hw_aspm_clkreq_enable(st + } else { + switch (tp->mac_version) { + case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: +- case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_71: ++ case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: + r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0); + break; + default: +@@ -4094,7 +4094,7 @@ static void rtl8169_cleanup(struct rtl81 + RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); + rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); + break; +- case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_71: ++ case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST: + rtl_enable_rxdvgate(tp); + fsleep(2000); + break; +@@ -4251,7 +4251,7 @@ static unsigned int rtl_quirk_packet_pad + + switch (tp->mac_version) { + case RTL_GIGA_MAC_VER_34: +- case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_71: ++ case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: + padto = max_t(unsigned int, padto, ETH_ZLEN); + break; + default: +@@ -5301,7 +5301,7 @@ static void rtl_hw_initialize(struct rtl + case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: + rtl_hw_init_8168g(tp); + break; +- case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_71: ++ case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: + rtl_hw_init_8125(tp); + break; + default: +@@ -5326,7 +5326,7 @@ static int rtl_jumbo_max(struct rtl8169_ + case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: + return JUMBO_6K; + /* RTL8125/8126 */ +- case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_71: ++ case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: + return JUMBO_16K; + default: + return JUMBO_9K; diff --git a/target/linux/generic/backport-6.12/780-38-v6.16-r8169-use-pci_prepare_to_sleep-in-rtl_shutdown.patch b/target/linux/generic/backport-6.12/780-38-v6.16-r8169-use-pci_prepare_to_sleep-in-rtl_shutdown.patch new file mode 100644 index 00000000000..784dc69953a --- /dev/null +++ b/target/linux/generic/backport-6.12/780-38-v6.16-r8169-use-pci_prepare_to_sleep-in-rtl_shutdown.patch @@ -0,0 +1,37 @@ +From b7ed5d5a78fccee96cf8919ac2c7a064c2f4c45b Mon Sep 17 00:00:00 2001 +From: Heiner Kallweit +Date: Mon, 21 Apr 2025 11:25:18 +0200 +Subject: [PATCH] r8169: use pci_prepare_to_sleep in rtl_shutdown + +Use pci_prepare_to_sleep() like PCI core does in pci_pm_suspend_noirq. +This aligns setting a low-power mode during shutdown with the handling +of the transition to system suspend. Also the transition to runtime +suspend uses pci_target_state() instead of setting D3hot unconditionally. + +Note: pci_prepare_to_sleep() uses device_may_wakeup() to check whether + device may generate wakeup events. So we don't lose anything by + not passing tp->saved_wolopts any longer. + +Signed-off-by: Heiner Kallweit +Reviewed-by: Jacob Keller +Link: https://patch.msgid.link/f573fdbd-ba6d-41c1-b68f-311d3c88db2c@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/realtek/r8169_main.c | 6 ++---- + 1 file changed, 2 insertions(+), 4 deletions(-) + +--- a/drivers/net/ethernet/realtek/r8169_main.c ++++ b/drivers/net/ethernet/realtek/r8169_main.c +@@ -5039,10 +5039,8 @@ static void rtl_shutdown(struct pci_dev + /* Restore original MAC address */ + rtl_rar_set(tp, tp->dev->perm_addr); + +- if (system_state == SYSTEM_POWER_OFF && !tp->dash_enabled) { +- pci_wake_from_d3(pdev, tp->saved_wolopts); +- pci_set_power_state(pdev, PCI_D3hot); +- } ++ if (system_state == SYSTEM_POWER_OFF && !tp->dash_enabled) ++ pci_prepare_to_sleep(pdev); + } + + static void rtl_remove_one(struct pci_dev *pdev) diff --git a/target/linux/generic/backport-6.12/780-39-v6.16-r8169-merge-chip-versions-70-and-71-RTL8126A.patch b/target/linux/generic/backport-6.12/780-39-v6.16-r8169-merge-chip-versions-70-and-71-RTL8126A.patch new file mode 100644 index 00000000000..da105f6fe3b --- /dev/null +++ b/target/linux/generic/backport-6.12/780-39-v6.16-r8169-merge-chip-versions-70-and-71-RTL8126A.patch @@ -0,0 +1,106 @@ +From 4dec0702b8627c364a0e1f2c5b249e06709a1c24 Mon Sep 17 00:00:00 2001 +From: Heiner Kallweit +Date: Fri, 18 Apr 2025 11:23:45 +0200 +Subject: [PATCH] r8169: merge chip versions 70 and 71 (RTL8126A) + +Handling of both chip versions is the same, only difference is +the firmware. So we can merge handling of both chip versions. + +Signed-off-by: Heiner Kallweit +Reviewed-by: Simon Horman +Link: https://patch.msgid.link/97d7ae79-d021-4b6b-b424-89e5e305b029@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/realtek/r8169.h | 1 - + drivers/net/ethernet/realtek/r8169_main.c | 15 ++++----------- + drivers/net/ethernet/realtek/r8169_phy_config.c | 1 - + 3 files changed, 4 insertions(+), 13 deletions(-) + +--- a/drivers/net/ethernet/realtek/r8169.h ++++ b/drivers/net/ethernet/realtek/r8169.h +@@ -72,7 +72,6 @@ enum mac_version { + RTL_GIGA_MAC_VER_65, + RTL_GIGA_MAC_VER_66, + RTL_GIGA_MAC_VER_70, +- RTL_GIGA_MAC_VER_71, + RTL_GIGA_MAC_NONE, + RTL_GIGA_MAC_VER_LAST = RTL_GIGA_MAC_NONE - 1 + }; +--- a/drivers/net/ethernet/realtek/r8169_main.c ++++ b/drivers/net/ethernet/realtek/r8169_main.c +@@ -99,7 +99,7 @@ static const struct rtl_chip_info { + const char *fw_name; + } rtl_chip_infos[] = { + /* 8126A family. */ +- { 0x7cf, 0x64a, RTL_GIGA_MAC_VER_71, "RTL8126A", FIRMWARE_8126A_3 }, ++ { 0x7cf, 0x64a, RTL_GIGA_MAC_VER_70, "RTL8126A", FIRMWARE_8126A_3 }, + { 0x7cf, 0x649, RTL_GIGA_MAC_VER_70, "RTL8126A", FIRMWARE_8126A_2 }, + + /* 8125BP family. */ +@@ -2939,7 +2939,6 @@ static void rtl_hw_aspm_clkreq_enable(st + rtl_mod_config5(tp, 0, ASPM_en); + switch (tp->mac_version) { + case RTL_GIGA_MAC_VER_70: +- case RTL_GIGA_MAC_VER_71: + val8 = RTL_R8(tp, INT_CFG0_8125) | INT_CFG0_CLKREQEN; + RTL_W8(tp, INT_CFG0_8125, val8); + break; +@@ -2971,7 +2970,6 @@ static void rtl_hw_aspm_clkreq_enable(st + + switch (tp->mac_version) { + case RTL_GIGA_MAC_VER_70: +- case RTL_GIGA_MAC_VER_71: + val8 = RTL_R8(tp, INT_CFG0_8125) & ~INT_CFG0_CLKREQEN; + RTL_W8(tp, INT_CFG0_8125, val8); + break; +@@ -3691,12 +3689,10 @@ static void rtl_hw_start_8125_common(str + /* disable new tx descriptor format */ + r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); + +- if (tp->mac_version == RTL_GIGA_MAC_VER_70 || +- tp->mac_version == RTL_GIGA_MAC_VER_71) ++ if (tp->mac_version == RTL_GIGA_MAC_VER_70) + RTL_W8(tp, 0xD8, RTL_R8(tp, 0xD8) & ~0x02); + +- if (tp->mac_version == RTL_GIGA_MAC_VER_70 || +- tp->mac_version == RTL_GIGA_MAC_VER_71) ++ if (tp->mac_version == RTL_GIGA_MAC_VER_70) + r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); + else if (tp->mac_version == RTL_GIGA_MAC_VER_63) + r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); +@@ -3714,8 +3710,7 @@ static void rtl_hw_start_8125_common(str + r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); + r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); + r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); +- if (tp->mac_version == RTL_GIGA_MAC_VER_70 || +- tp->mac_version == RTL_GIGA_MAC_VER_71) ++ if (tp->mac_version == RTL_GIGA_MAC_VER_70) + r8168_mac_ocp_modify(tp, 0xea1c, 0x0300, 0x0000); + else + r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); +@@ -3838,7 +3833,6 @@ static void rtl_hw_config(struct rtl8169 + [RTL_GIGA_MAC_VER_65] = rtl_hw_start_8125d, + [RTL_GIGA_MAC_VER_66] = rtl_hw_start_8125d, + [RTL_GIGA_MAC_VER_70] = rtl_hw_start_8126a, +- [RTL_GIGA_MAC_VER_71] = rtl_hw_start_8126a, + }; + + if (hw_configs[tp->mac_version]) +@@ -3862,7 +3856,6 @@ static void rtl_hw_start_8125(struct rtl + break; + case RTL_GIGA_MAC_VER_63: + case RTL_GIGA_MAC_VER_70: +- case RTL_GIGA_MAC_VER_71: + for (i = 0xa00; i < 0xa80; i += 4) + RTL_W32(tp, i, 0); + RTL_W16(tp, INT_CFG1_8125, 0x0000); +--- a/drivers/net/ethernet/realtek/r8169_phy_config.c ++++ b/drivers/net/ethernet/realtek/r8169_phy_config.c +@@ -1183,7 +1183,6 @@ void r8169_hw_phy_config(struct rtl8169_ + [RTL_GIGA_MAC_VER_65] = rtl8125d_hw_phy_config, + [RTL_GIGA_MAC_VER_66] = rtl8125bp_hw_phy_config, + [RTL_GIGA_MAC_VER_70] = rtl8126a_hw_phy_config, +- [RTL_GIGA_MAC_VER_71] = rtl8126a_hw_phy_config, + }; + + if (phy_configs[ver]) diff --git a/target/linux/generic/backport-6.12/780-40-v6.16-r8169-merge-chip-versions-64-and-65-RTL8125D.patch b/target/linux/generic/backport-6.12/780-40-v6.16-r8169-merge-chip-versions-64-and-65-RTL8125D.patch new file mode 100644 index 00000000000..a5e4c123a20 --- /dev/null +++ b/target/linux/generic/backport-6.12/780-40-v6.16-r8169-merge-chip-versions-64-and-65-RTL8125D.patch @@ -0,0 +1,65 @@ +From f372ef6ed5a6b0401c884561d4bba1843e54d46a Mon Sep 17 00:00:00 2001 +From: Heiner Kallweit +Date: Fri, 18 Apr 2025 11:24:30 +0200 +Subject: [PATCH] r8169: merge chip versions 64 and 65 (RTL8125D) + +Handling of both chip versions is the same, only difference is +the firmware. So we can merge handling of both chip versions. + +Signed-off-by: Heiner Kallweit +Reviewed-by: Simon Horman +Link: https://patch.msgid.link/0baad123-c679-4154-923f-fdc12783e900@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/realtek/r8169.h | 1 - + drivers/net/ethernet/realtek/r8169_main.c | 4 +--- + drivers/net/ethernet/realtek/r8169_phy_config.c | 1 - + 3 files changed, 1 insertion(+), 5 deletions(-) + +--- a/drivers/net/ethernet/realtek/r8169.h ++++ b/drivers/net/ethernet/realtek/r8169.h +@@ -69,7 +69,6 @@ enum mac_version { + RTL_GIGA_MAC_VER_61, + RTL_GIGA_MAC_VER_63, + RTL_GIGA_MAC_VER_64, +- RTL_GIGA_MAC_VER_65, + RTL_GIGA_MAC_VER_66, + RTL_GIGA_MAC_VER_70, + RTL_GIGA_MAC_NONE, +--- a/drivers/net/ethernet/realtek/r8169_main.c ++++ b/drivers/net/ethernet/realtek/r8169_main.c +@@ -106,7 +106,7 @@ static const struct rtl_chip_info { + { 0x7cf, 0x681, RTL_GIGA_MAC_VER_66, "RTL8125BP", FIRMWARE_8125BP_2 }, + + /* 8125D family. */ +- { 0x7cf, 0x689, RTL_GIGA_MAC_VER_65, "RTL8125D", FIRMWARE_8125D_2 }, ++ { 0x7cf, 0x689, RTL_GIGA_MAC_VER_64, "RTL8125D", FIRMWARE_8125D_2 }, + { 0x7cf, 0x688, RTL_GIGA_MAC_VER_64, "RTL8125D", FIRMWARE_8125D_1 }, + + /* 8125B family. */ +@@ -3830,7 +3830,6 @@ static void rtl_hw_config(struct rtl8169 + [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2, + [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, + [RTL_GIGA_MAC_VER_64] = rtl_hw_start_8125d, +- [RTL_GIGA_MAC_VER_65] = rtl_hw_start_8125d, + [RTL_GIGA_MAC_VER_66] = rtl_hw_start_8125d, + [RTL_GIGA_MAC_VER_70] = rtl_hw_start_8126a, + }; +@@ -3849,7 +3848,6 @@ static void rtl_hw_start_8125(struct rtl + switch (tp->mac_version) { + case RTL_GIGA_MAC_VER_61: + case RTL_GIGA_MAC_VER_64: +- case RTL_GIGA_MAC_VER_65: + case RTL_GIGA_MAC_VER_66: + for (i = 0xa00; i < 0xb00; i += 4) + RTL_W32(tp, i, 0); +--- a/drivers/net/ethernet/realtek/r8169_phy_config.c ++++ b/drivers/net/ethernet/realtek/r8169_phy_config.c +@@ -1180,7 +1180,6 @@ void r8169_hw_phy_config(struct rtl8169_ + [RTL_GIGA_MAC_VER_61] = rtl8125a_2_hw_phy_config, + [RTL_GIGA_MAC_VER_63] = rtl8125b_hw_phy_config, + [RTL_GIGA_MAC_VER_64] = rtl8125d_hw_phy_config, +- [RTL_GIGA_MAC_VER_65] = rtl8125d_hw_phy_config, + [RTL_GIGA_MAC_VER_66] = rtl8125bp_hw_phy_config, + [RTL_GIGA_MAC_VER_70] = rtl8126a_hw_phy_config, + }; diff --git a/target/linux/generic/backport-6.12/780-41-v6.16-r8169-merge-chip-versions-52-and-53-RTL8117.patch b/target/linux/generic/backport-6.12/780-41-v6.16-r8169-merge-chip-versions-52-and-53-RTL8117.patch new file mode 100644 index 00000000000..7ed72a98973 --- /dev/null +++ b/target/linux/generic/backport-6.12/780-41-v6.16-r8169-merge-chip-versions-52-and-53-RTL8117.patch @@ -0,0 +1,113 @@ +From 4f51e7d370a04122fa78470b031d6487c52298b1 Mon Sep 17 00:00:00 2001 +From: Heiner Kallweit +Date: Fri, 18 Apr 2025 11:25:17 +0200 +Subject: [PATCH] r8169: merge chip versions 52 and 53 (RTL8117) + +Handling of both chip versions is the same, only difference is +the firmware. So we can merge handling of both chip versions. + +Signed-off-by: Heiner Kallweit +Reviewed-by: Simon Horman +Link: https://patch.msgid.link/ae866b71-c904-434e-befb-848c831e33ff@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/realtek/r8169.h | 1 - + drivers/net/ethernet/realtek/r8169_main.c | 17 +++++++---------- + drivers/net/ethernet/realtek/r8169_phy_config.c | 1 - + 3 files changed, 7 insertions(+), 12 deletions(-) + +--- a/drivers/net/ethernet/realtek/r8169.h ++++ b/drivers/net/ethernet/realtek/r8169.h +@@ -64,7 +64,6 @@ enum mac_version { + /* support for RTL_GIGA_MAC_VER_50 has been removed */ + RTL_GIGA_MAC_VER_51, + RTL_GIGA_MAC_VER_52, +- RTL_GIGA_MAC_VER_53, + /* support for RTL_GIGA_MAC_VER_60 has been removed */ + RTL_GIGA_MAC_VER_61, + RTL_GIGA_MAC_VER_63, +--- a/drivers/net/ethernet/realtek/r8169_main.c ++++ b/drivers/net/ethernet/realtek/r8169_main.c +@@ -116,7 +116,7 @@ static const struct rtl_chip_info { + { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61, "RTL8125A", FIRMWARE_8125A_3 }, + + /* RTL8117 */ +- { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53, "RTL8168fp/RTL8117" }, ++ { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_52, "RTL8168fp/RTL8117" }, + { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52, "RTL8168fp/RTL8117", + FIRMWARE_8168FP_3 }, + +@@ -830,7 +830,7 @@ static bool rtl_is_8168evl_up(struct rtl + { + return tp->mac_version >= RTL_GIGA_MAC_VER_34 && + tp->mac_version != RTL_GIGA_MAC_VER_39 && +- tp->mac_version <= RTL_GIGA_MAC_VER_53; ++ tp->mac_version <= RTL_GIGA_MAC_VER_52; + } + + static bool rtl_supports_eee(struct rtl8169_private *tp) +@@ -998,9 +998,7 @@ void r8169_get_led_name(struct rtl8169_p + static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type) + { + /* based on RTL8168FP_OOBMAC_BASE in vendor driver */ +- if (type == ERIAR_OOB && +- (tp->mac_version == RTL_GIGA_MAC_VER_52 || +- tp->mac_version == RTL_GIGA_MAC_VER_53)) ++ if (type == ERIAR_OOB && tp->mac_version == RTL_GIGA_MAC_VER_52) + *cmd |= 0xf70 << 18; + } + +@@ -1500,7 +1498,7 @@ static enum rtl_dash_type rtl_get_dash_t + case RTL_GIGA_MAC_VER_28: + case RTL_GIGA_MAC_VER_31: + return RTL_DASH_DP; +- case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: ++ case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_52: + return RTL_DASH_EP; + case RTL_GIGA_MAC_VER_66: + return RTL_DASH_25_BP; +@@ -2485,7 +2483,7 @@ static void rtl_init_rxcfg(struct rtl816 + case RTL_GIGA_MAC_VER_38: + RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); + break; +- case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: ++ case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52: + RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); + break; + case RTL_GIGA_MAC_VER_61: +@@ -2616,7 +2614,7 @@ DECLARE_RTL_COND(rtl_rxtx_empty_cond_2) + static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp) + { + switch (tp->mac_version) { +- case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: ++ case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52: + rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42); + rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); + break; +@@ -3826,7 +3824,6 @@ static void rtl_hw_config(struct rtl8169 + [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, + [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, + [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, +- [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117, + [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2, + [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, + [RTL_GIGA_MAC_VER_64] = rtl_hw_start_8125d, +@@ -5284,7 +5281,7 @@ static void rtl_hw_init_8125(struct rtl8 + static void rtl_hw_initialize(struct rtl8169_private *tp) + { + switch (tp->mac_version) { +- case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: ++ case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_52: + rtl8168ep_stop_cmac(tp); + fallthrough; + case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: +--- a/drivers/net/ethernet/realtek/r8169_phy_config.c ++++ b/drivers/net/ethernet/realtek/r8169_phy_config.c +@@ -1176,7 +1176,6 @@ void r8169_hw_phy_config(struct rtl8169_ + [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config, + [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config, + [RTL_GIGA_MAC_VER_52] = rtl8117_hw_phy_config, +- [RTL_GIGA_MAC_VER_53] = rtl8117_hw_phy_config, + [RTL_GIGA_MAC_VER_61] = rtl8125a_2_hw_phy_config, + [RTL_GIGA_MAC_VER_63] = rtl8125b_hw_phy_config, + [RTL_GIGA_MAC_VER_64] = rtl8125d_hw_phy_config, diff --git a/target/linux/generic/backport-6.12/780-42-v6.16-r8169-add-support-for-RTL8127A.patch b/target/linux/generic/backport-6.12/780-42-v6.16-r8169-add-support-for-RTL8127A.patch new file mode 100644 index 00000000000..37a2d8667ec --- /dev/null +++ b/target/linux/generic/backport-6.12/780-42-v6.16-r8169-add-support-for-RTL8127A.patch @@ -0,0 +1,323 @@ +From f24f7b2f3af9e008ded20f804d7829ee2efd43f2 Mon Sep 17 00:00:00 2001 +From: ChunHao Lin +Date: Thu, 15 May 2025 17:53:03 +0800 +Subject: [PATCH] r8169: add support for RTL8127A + +This adds support for 10Gbs chip RTL8127A. + +Signed-off-by: ChunHao Lin +Reviewed-by: Heiner Kallweit +Link: https://patch.msgid.link/20250515095303.3138-1-hau@realtek.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/realtek/r8169.h | 1 + + drivers/net/ethernet/realtek/r8169_main.c | 29 ++- + .../net/ethernet/realtek/r8169_phy_config.c | 166 ++++++++++++++++++ + 3 files changed, 193 insertions(+), 3 deletions(-) + +--- a/drivers/net/ethernet/realtek/r8169.h ++++ b/drivers/net/ethernet/realtek/r8169.h +@@ -70,6 +70,7 @@ enum mac_version { + RTL_GIGA_MAC_VER_64, + RTL_GIGA_MAC_VER_66, + RTL_GIGA_MAC_VER_70, ++ RTL_GIGA_MAC_VER_80, + RTL_GIGA_MAC_NONE, + RTL_GIGA_MAC_VER_LAST = RTL_GIGA_MAC_NONE - 1 + }; +--- a/drivers/net/ethernet/realtek/r8169_main.c ++++ b/drivers/net/ethernet/realtek/r8169_main.c +@@ -60,6 +60,7 @@ + #define FIRMWARE_8125BP_2 "rtl_nic/rtl8125bp-2.fw" + #define FIRMWARE_8126A_2 "rtl_nic/rtl8126a-2.fw" + #define FIRMWARE_8126A_3 "rtl_nic/rtl8126a-3.fw" ++#define FIRMWARE_8127A_1 "rtl_nic/rtl8127a-1.fw" + + #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ + #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ +@@ -98,6 +99,9 @@ static const struct rtl_chip_info { + const char *name; + const char *fw_name; + } rtl_chip_infos[] = { ++ /* 8127A family. */ ++ { 0x7cf, 0x6c9, RTL_GIGA_MAC_VER_80, "RTL8127A", FIRMWARE_8127A_1 }, ++ + /* 8126A family. */ + { 0x7cf, 0x64a, RTL_GIGA_MAC_VER_70, "RTL8126A", FIRMWARE_8126A_3 }, + { 0x7cf, 0x649, RTL_GIGA_MAC_VER_70, "RTL8126A", FIRMWARE_8126A_2 }, +@@ -222,8 +226,10 @@ static const struct pci_device_id rtl816 + { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, + { PCI_VDEVICE(REALTEK, 0x8125) }, + { PCI_VDEVICE(REALTEK, 0x8126) }, ++ { PCI_VDEVICE(REALTEK, 0x8127) }, + { PCI_VDEVICE(REALTEK, 0x3000) }, + { PCI_VDEVICE(REALTEK, 0x5000) }, ++ { PCI_VDEVICE(REALTEK, 0x0e10) }, + {} + }; + +@@ -769,6 +775,7 @@ MODULE_FIRMWARE(FIRMWARE_8125D_2); + MODULE_FIRMWARE(FIRMWARE_8125BP_2); + MODULE_FIRMWARE(FIRMWARE_8126A_2); + MODULE_FIRMWARE(FIRMWARE_8126A_3); ++MODULE_FIRMWARE(FIRMWARE_8127A_1); + + static inline struct device *tp_to_dev(struct rtl8169_private *tp) + { +@@ -2937,6 +2944,7 @@ static void rtl_hw_aspm_clkreq_enable(st + rtl_mod_config5(tp, 0, ASPM_en); + switch (tp->mac_version) { + case RTL_GIGA_MAC_VER_70: ++ case RTL_GIGA_MAC_VER_80: + val8 = RTL_R8(tp, INT_CFG0_8125) | INT_CFG0_CLKREQEN; + RTL_W8(tp, INT_CFG0_8125, val8); + break; +@@ -2968,6 +2976,7 @@ static void rtl_hw_aspm_clkreq_enable(st + + switch (tp->mac_version) { + case RTL_GIGA_MAC_VER_70: ++ case RTL_GIGA_MAC_VER_80: + val8 = RTL_R8(tp, INT_CFG0_8125) & ~INT_CFG0_CLKREQEN; + RTL_W8(tp, INT_CFG0_8125, val8); + break; +@@ -3687,10 +3696,13 @@ static void rtl_hw_start_8125_common(str + /* disable new tx descriptor format */ + r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); + +- if (tp->mac_version == RTL_GIGA_MAC_VER_70) ++ if (tp->mac_version == RTL_GIGA_MAC_VER_70 || ++ tp->mac_version == RTL_GIGA_MAC_VER_80) + RTL_W8(tp, 0xD8, RTL_R8(tp, 0xD8) & ~0x02); + +- if (tp->mac_version == RTL_GIGA_MAC_VER_70) ++ if (tp->mac_version == RTL_GIGA_MAC_VER_80) ++ r8168_mac_ocp_modify(tp, 0xe614, 0x0f00, 0x0f00); ++ else if (tp->mac_version == RTL_GIGA_MAC_VER_70) + r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); + else if (tp->mac_version == RTL_GIGA_MAC_VER_63) + r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); +@@ -3708,7 +3720,8 @@ static void rtl_hw_start_8125_common(str + r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); + r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); + r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); +- if (tp->mac_version == RTL_GIGA_MAC_VER_70) ++ if (tp->mac_version == RTL_GIGA_MAC_VER_70 || ++ tp->mac_version == RTL_GIGA_MAC_VER_80) + r8168_mac_ocp_modify(tp, 0xea1c, 0x0300, 0x0000); + else + r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); +@@ -3786,6 +3799,12 @@ static void rtl_hw_start_8126a(struct rt + rtl_hw_start_8125_common(tp); + } + ++static void rtl_hw_start_8127a(struct rtl8169_private *tp) ++{ ++ rtl_set_def_aspm_entry_latency(tp); ++ rtl_hw_start_8125_common(tp); ++} ++ + static void rtl_hw_config(struct rtl8169_private *tp) + { + static const rtl_generic_fct hw_configs[] = { +@@ -3829,6 +3848,7 @@ static void rtl_hw_config(struct rtl8169 + [RTL_GIGA_MAC_VER_64] = rtl_hw_start_8125d, + [RTL_GIGA_MAC_VER_66] = rtl_hw_start_8125d, + [RTL_GIGA_MAC_VER_70] = rtl_hw_start_8126a, ++ [RTL_GIGA_MAC_VER_80] = rtl_hw_start_8127a, + }; + + if (hw_configs[tp->mac_version]) +@@ -3846,8 +3866,11 @@ static void rtl_hw_start_8125(struct rtl + case RTL_GIGA_MAC_VER_61: + case RTL_GIGA_MAC_VER_64: + case RTL_GIGA_MAC_VER_66: ++ case RTL_GIGA_MAC_VER_80: + for (i = 0xa00; i < 0xb00; i += 4) + RTL_W32(tp, i, 0); ++ if (tp->mac_version == RTL_GIGA_MAC_VER_80) ++ RTL_W16(tp, INT_CFG1_8125, 0x0000); + break; + case RTL_GIGA_MAC_VER_63: + case RTL_GIGA_MAC_VER_70: +--- a/drivers/net/ethernet/realtek/r8169_phy_config.c ++++ b/drivers/net/ethernet/realtek/r8169_phy_config.c +@@ -1130,6 +1130,171 @@ static void rtl8126a_hw_phy_config(struc + rtl8125_common_config_eee_phy(phydev); + } + ++static void rtl8127a_1_hw_phy_config(struct rtl8169_private *tp, ++ struct phy_device *phydev) ++{ ++ r8169_apply_firmware(tp); ++ rtl8168g_enable_gphy_10m(phydev); ++ ++ r8168g_phy_param(phydev, 0x8415, 0xff00, 0x9300); ++ r8168g_phy_param(phydev, 0x81a3, 0xff00, 0x0f00); ++ r8168g_phy_param(phydev, 0x81ae, 0xff00, 0x0f00); ++ r8168g_phy_param(phydev, 0x81b9, 0xff00, 0xb900); ++ rtl8125_phy_param(phydev, 0x83b0, 0x0e00, 0x0000); ++ rtl8125_phy_param(phydev, 0x83C5, 0x0e00, 0x0000); ++ rtl8125_phy_param(phydev, 0x83da, 0x0e00, 0x0000); ++ rtl8125_phy_param(phydev, 0x83ef, 0x0e00, 0x0000); ++ phy_modify_paged(phydev, 0x0bf3, 0x14, 0x01f0, 0x0160); ++ phy_modify_paged(phydev, 0x0bf3, 0x15, 0x001f, 0x0014); ++ phy_modify_paged(phydev, 0x0bf2, 0x14, 0x6000, 0x0000); ++ phy_modify_paged(phydev, 0x0bf2, 0x16, 0xc000, 0x0000); ++ phy_modify_paged(phydev, 0x0bf2, 0x14, 0x1fff, 0x0187); ++ phy_modify_paged(phydev, 0x0bf2, 0x15, 0x003f, 0x0003); ++ ++ r8168g_phy_param(phydev, 0x8173, 0xffff, 0x8620); ++ r8168g_phy_param(phydev, 0x8175, 0xffff, 0x8671); ++ r8168g_phy_param(phydev, 0x817c, 0x0000, 0x2000); ++ r8168g_phy_param(phydev, 0x8187, 0x0000, 0x2000); ++ r8168g_phy_param(phydev, 0x8192, 0x0000, 0x2000); ++ r8168g_phy_param(phydev, 0x819d, 0x0000, 0x2000); ++ r8168g_phy_param(phydev, 0x81a8, 0x2000, 0x0000); ++ r8168g_phy_param(phydev, 0x81b3, 0x2000, 0x0000); ++ r8168g_phy_param(phydev, 0x81be, 0x0000, 0x2000); ++ r8168g_phy_param(phydev, 0x817d, 0xff00, 0xa600); ++ r8168g_phy_param(phydev, 0x8188, 0xff00, 0xa600); ++ r8168g_phy_param(phydev, 0x8193, 0xff00, 0xa600); ++ r8168g_phy_param(phydev, 0x819e, 0xff00, 0xa600); ++ r8168g_phy_param(phydev, 0x81a9, 0xff00, 0x1400); ++ r8168g_phy_param(phydev, 0x81b4, 0xff00, 0x1400); ++ r8168g_phy_param(phydev, 0x81bf, 0xff00, 0xa600); ++ ++ phy_modify_paged(phydev, 0x0aea, 0x15, 0x0028, 0x0000); ++ ++ rtl8125_phy_param(phydev, 0x84f0, 0xffff, 0x201c); ++ rtl8125_phy_param(phydev, 0x84f2, 0xffff, 0x3117); ++ ++ phy_write_paged(phydev, 0x0aec, 0x13, 0x0000); ++ phy_write_paged(phydev, 0x0ae2, 0x10, 0xffff); ++ phy_write_paged(phydev, 0x0aec, 0x17, 0xffff); ++ phy_write_paged(phydev, 0x0aed, 0x11, 0xffff); ++ phy_write_paged(phydev, 0x0aec, 0x14, 0x0000); ++ phy_modify_paged(phydev, 0x0aed, 0x10, 0x0001, 0x0000); ++ phy_write_paged(phydev, 0x0adb, 0x14, 0x0150); ++ rtl8125_phy_param(phydev, 0x8197, 0xff00, 0x5000); ++ rtl8125_phy_param(phydev, 0x8231, 0xff00, 0x5000); ++ rtl8125_phy_param(phydev, 0x82cb, 0xff00, 0x5000); ++ rtl8125_phy_param(phydev, 0x82cd, 0xff00, 0x5700); ++ rtl8125_phy_param(phydev, 0x8233, 0xff00, 0x5700); ++ rtl8125_phy_param(phydev, 0x8199, 0xff00, 0x5700); ++ ++ rtl8125_phy_param(phydev, 0x815a, 0xffff, 0x0150); ++ rtl8125_phy_param(phydev, 0x81f4, 0xffff, 0x0150); ++ rtl8125_phy_param(phydev, 0x828e, 0xffff, 0x0150); ++ rtl8125_phy_param(phydev, 0x81b1, 0xffff, 0x0000); ++ rtl8125_phy_param(phydev, 0x824b, 0xffff, 0x0000); ++ rtl8125_phy_param(phydev, 0x82e5, 0xffff, 0x0000); ++ ++ rtl8125_phy_param(phydev, 0x84f7, 0xff00, 0x2800); ++ phy_modify_paged(phydev, 0x0aec, 0x11, 0x0000, 0x1000); ++ rtl8125_phy_param(phydev, 0x81b3, 0xff00, 0xad00); ++ rtl8125_phy_param(phydev, 0x824d, 0xff00, 0xad00); ++ rtl8125_phy_param(phydev, 0x82e7, 0xff00, 0xad00); ++ phy_modify_paged(phydev, 0x0ae4, 0x17, 0x000f, 0x0001); ++ rtl8125_phy_param(phydev, 0x82ce, 0xf000, 0x4000); ++ ++ rtl8125_phy_param(phydev, 0x84ac, 0xffff, 0x0000); ++ rtl8125_phy_param(phydev, 0x84ae, 0xffff, 0x0000); ++ rtl8125_phy_param(phydev, 0x84b0, 0xffff, 0xf818); ++ rtl8125_phy_param(phydev, 0x84b2, 0xff00, 0x6000); ++ ++ rtl8125_phy_param(phydev, 0x8ffc, 0xffff, 0x6008); ++ rtl8125_phy_param(phydev, 0x8ffe, 0xffff, 0xf450); ++ ++ rtl8125_phy_param(phydev, 0x8015, 0x0000, 0x0200); ++ rtl8125_phy_param(phydev, 0x8016, 0x0800, 0x0000); ++ rtl8125_phy_param(phydev, 0x8fe6, 0xff00, 0x0800); ++ rtl8125_phy_param(phydev, 0x8fe4, 0xffff, 0x2114); ++ ++ rtl8125_phy_param(phydev, 0x8647, 0xffff, 0xa7b1); ++ rtl8125_phy_param(phydev, 0x8649, 0xffff, 0xbbca); ++ rtl8125_phy_param(phydev, 0x864b, 0xff00, 0xdc00); ++ ++ rtl8125_phy_param(phydev, 0x8154, 0xc000, 0x4000); ++ rtl8125_phy_param(phydev, 0x8158, 0xc000, 0x0000); ++ ++ rtl8125_phy_param(phydev, 0x826c, 0xffff, 0xffff); ++ rtl8125_phy_param(phydev, 0x826e, 0xffff, 0xffff); ++ ++ rtl8125_phy_param(phydev, 0x8872, 0xff00, 0x0e00); ++ r8168g_phy_param(phydev, 0x8012, 0x0000, 0x0800); ++ r8168g_phy_param(phydev, 0x8012, 0x0000, 0x4000); ++ phy_modify_paged(phydev, 0x0b57, 0x13, 0x0000, 0x0001); ++ r8168g_phy_param(phydev, 0x834a, 0xff00, 0x0700); ++ rtl8125_phy_param(phydev, 0x8217, 0x3f00, 0x2a00); ++ r8168g_phy_param(phydev, 0x81b1, 0xff00, 0x0b00); ++ rtl8125_phy_param(phydev, 0x8fed, 0xff00, 0x4e00); ++ ++ rtl8125_phy_param(phydev, 0x88ac, 0xff00, 0x2300); ++ phy_modify_paged(phydev, 0x0bf0, 0x16, 0x0000, 0x3800); ++ rtl8125_phy_param(phydev, 0x88de, 0xff00, 0x0000); ++ rtl8125_phy_param(phydev, 0x80b4, 0xffff, 0x5195); ++ ++ r8168g_phy_param(phydev, 0x8370, 0xffff, 0x8671); ++ r8168g_phy_param(phydev, 0x8372, 0xffff, 0x86c8); ++ ++ r8168g_phy_param(phydev, 0x8401, 0xffff, 0x86c8); ++ r8168g_phy_param(phydev, 0x8403, 0xffff, 0x86da); ++ r8168g_phy_param(phydev, 0x8406, 0x1800, 0x1000); ++ r8168g_phy_param(phydev, 0x8408, 0x1800, 0x1000); ++ r8168g_phy_param(phydev, 0x840a, 0x1800, 0x1000); ++ r8168g_phy_param(phydev, 0x840c, 0x1800, 0x1000); ++ r8168g_phy_param(phydev, 0x840e, 0x1800, 0x1000); ++ r8168g_phy_param(phydev, 0x8410, 0x1800, 0x1000); ++ r8168g_phy_param(phydev, 0x8412, 0x1800, 0x1000); ++ r8168g_phy_param(phydev, 0x8414, 0x1800, 0x1000); ++ r8168g_phy_param(phydev, 0x8416, 0x1800, 0x1000); ++ ++ r8168g_phy_param(phydev, 0x82bd, 0xffff, 0x1f40); ++ ++ phy_modify_paged(phydev, 0x0bfb, 0x12, 0x07ff, 0x0328); ++ phy_write_paged(phydev, 0x0bfb, 0x13, 0x3e14); ++ ++ r8168g_phy_param(phydev, 0x81c4, 0xffff, 0x003b); ++ r8168g_phy_param(phydev, 0x81c6, 0xffff, 0x0086); ++ r8168g_phy_param(phydev, 0x81c8, 0xffff, 0x00b7); ++ r8168g_phy_param(phydev, 0x81ca, 0xffff, 0x00db); ++ r8168g_phy_param(phydev, 0x81cc, 0xffff, 0x00fe); ++ r8168g_phy_param(phydev, 0x81ce, 0xffff, 0x00fe); ++ r8168g_phy_param(phydev, 0x81d0, 0xffff, 0x00fe); ++ r8168g_phy_param(phydev, 0x81d2, 0xffff, 0x00fe); ++ r8168g_phy_param(phydev, 0x81d4, 0xffff, 0x00c3); ++ r8168g_phy_param(phydev, 0x81d6, 0xffff, 0x0078); ++ r8168g_phy_param(phydev, 0x81d8, 0xffff, 0x0047); ++ r8168g_phy_param(phydev, 0x81da, 0xffff, 0x0023); ++ ++ rtl8125_phy_param(phydev, 0x88d7, 0xffff, 0x01a0); ++ rtl8125_phy_param(phydev, 0x88d9, 0xffff, 0x01a0); ++ rtl8125_phy_param(phydev, 0x8ffa, 0xffff, 0x002a); ++ ++ rtl8125_phy_param(phydev, 0x8fee, 0xffff, 0xffdf); ++ rtl8125_phy_param(phydev, 0x8ff0, 0xffff, 0xffff); ++ rtl8125_phy_param(phydev, 0x8ff2, 0xffff, 0x0a4a); ++ rtl8125_phy_param(phydev, 0x8ff4, 0xffff, 0xaa5a); ++ rtl8125_phy_param(phydev, 0x8ff6, 0xffff, 0x0a4a); ++ ++ rtl8125_phy_param(phydev, 0x8ff8, 0xffff, 0xaa5a); ++ rtl8125_phy_param(phydev, 0x88d5, 0xff00, 0x0200); ++ ++ r8168g_phy_param(phydev, 0x84bb, 0xff00, 0x0a00); ++ r8168g_phy_param(phydev, 0x84c0, 0xff00, 0x1600); ++ ++ phy_modify_paged(phydev, 0x0a43, 0x10, 0x0000, 0x0003); ++ ++ rtl8125_legacy_force_mode(phydev); ++ rtl8168g_disable_aldps(phydev); ++ rtl8125_common_config_eee_phy(phydev); ++} ++ + void r8169_hw_phy_config(struct rtl8169_private *tp, struct phy_device *phydev, + enum mac_version ver) + { +@@ -1181,6 +1346,7 @@ void r8169_hw_phy_config(struct rtl8169_ + [RTL_GIGA_MAC_VER_64] = rtl8125d_hw_phy_config, + [RTL_GIGA_MAC_VER_66] = rtl8125bp_hw_phy_config, + [RTL_GIGA_MAC_VER_70] = rtl8126a_hw_phy_config, ++ [RTL_GIGA_MAC_VER_80] = rtl8127a_1_hw_phy_config, + }; + + if (phy_configs[ver]) diff --git a/target/linux/generic/backport-6.6/780-57-v6.16-r8169-add-helper-rtl_csi_mod-for-accessing-extended.patch b/target/linux/generic/backport-6.6/780-57-v6.16-r8169-add-helper-rtl_csi_mod-for-accessing-extended.patch new file mode 100644 index 00000000000..0c5db62c9b5 --- /dev/null +++ b/target/linux/generic/backport-6.6/780-57-v6.16-r8169-add-helper-rtl_csi_mod-for-accessing-extended.patch @@ -0,0 +1,74 @@ +From 8c40d99e5f43e0545a3f4fea9156313847e2eb79 Mon Sep 17 00:00:00 2001 +From: Heiner Kallweit +Date: Wed, 9 Apr 2025 21:05:37 +0200 +Subject: [PATCH] r8169: add helper rtl_csi_mod for accessing extended config + space + +Add a helper for the Realtek-specific mechanism for accessing extended +config space if native access isn't possible. +This avoids code duplication. + +Signed-off-by: Heiner Kallweit +Link: https://patch.msgid.link/b368fd91-57d7-4cb5-9342-98b4d8fe9aea@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/realtek/r8169_main.c | 26 ++++++++++++++--------- + 1 file changed, 16 insertions(+), 10 deletions(-) + +--- a/drivers/net/ethernet/realtek/r8169_main.c ++++ b/drivers/net/ethernet/realtek/r8169_main.c +@@ -2856,10 +2856,23 @@ static u32 rtl_csi_read(struct rtl8169_p + RTL_R32(tp, CSIDR) : ~0; + } + ++static void rtl_csi_mod(struct rtl8169_private *tp, int addr, ++ u32 mask, u32 set) ++{ ++ u32 val; ++ ++ WARN(addr % 4, "Invalid CSI address %#x\n", addr); ++ ++ netdev_notice_once(tp->dev, ++ "No native access to PCI extended config space, falling back to CSI\n"); ++ ++ val = rtl_csi_read(tp, addr); ++ rtl_csi_write(tp, addr, (val & ~mask) | set); ++} ++ + static void rtl_disable_zrxdc_timeout(struct rtl8169_private *tp) + { + struct pci_dev *pdev = tp->pci_dev; +- u32 csi; + int rc; + u8 val; + +@@ -2876,16 +2889,12 @@ static void rtl_disable_zrxdc_timeout(st + } + } + +- netdev_notice_once(tp->dev, +- "No native access to PCI extended config space, falling back to CSI\n"); +- csi = rtl_csi_read(tp, RTL_GEN3_RELATED_OFF); +- rtl_csi_write(tp, RTL_GEN3_RELATED_OFF, csi & ~RTL_GEN3_ZRXDC_NONCOMPL); ++ rtl_csi_mod(tp, RTL_GEN3_RELATED_OFF, RTL_GEN3_ZRXDC_NONCOMPL, 0); + } + + static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val) + { + struct pci_dev *pdev = tp->pci_dev; +- u32 csi; + + /* According to Realtek the value at config space address 0x070f + * controls the L0s/L1 entrance latency. We try standard ECAM access +@@ -2897,10 +2906,7 @@ static void rtl_set_aspm_entry_latency(s + pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) + return; + +- netdev_notice_once(tp->dev, +- "No native access to PCI extended config space, falling back to CSI\n"); +- csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; +- rtl_csi_write(tp, 0x070c, csi | val << 24); ++ rtl_csi_mod(tp, 0x070c, 0xff000000, val << 24); + } + + static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) diff --git a/target/linux/generic/backport-6.6/780-58-v6.16-r8169-add-helper-rtl8125_phy_param.patch b/target/linux/generic/backport-6.6/780-58-v6.16-r8169-add-helper-rtl8125_phy_param.patch new file mode 100644 index 00000000000..30ebb4b6f48 --- /dev/null +++ b/target/linux/generic/backport-6.6/780-58-v6.16-r8169-add-helper-rtl8125_phy_param.patch @@ -0,0 +1,82 @@ +From 0c49baf099ba2147a6ff3bbdc3197c6ddbee5469 Mon Sep 17 00:00:00 2001 +From: Heiner Kallweit +Date: Wed, 9 Apr 2025 21:14:47 +0200 +Subject: [PATCH] r8169: add helper rtl8125_phy_param + +The integrated PHY's of RTL8125/8126 have an own mechanism to access +PHY parameters, similar to what r8168g_phy_param does on earlier PHY +versions. Add helper rtl8125_phy_param to simplify the code. + +Signed-off-by: Heiner Kallweit +Link: https://patch.msgid.link/847b7356-12d6-441b-ade9-4b6e1539b84a@gmail.com +Signed-off-by: Jakub Kicinski +--- + .../net/ethernet/realtek/r8169_phy_config.c | 36 +++++++++---------- + 1 file changed, 16 insertions(+), 20 deletions(-) + +--- a/drivers/net/ethernet/realtek/r8169_phy_config.c ++++ b/drivers/net/ethernet/realtek/r8169_phy_config.c +@@ -50,6 +50,15 @@ static void r8168g_phy_param(struct phy_ + phy_restore_page(phydev, oldpage, 0); + } + ++static void rtl8125_phy_param(struct phy_device *phydev, u16 parm, ++ u16 mask, u16 val) ++{ ++ phy_lock_mdio_bus(phydev); ++ __phy_write_mmd(phydev, MDIO_MMD_VEND2, 0xb87c, parm); ++ __phy_modify_mmd(phydev, MDIO_MMD_VEND2, 0xb87e, mask, val); ++ phy_unlock_mdio_bus(phydev); ++} ++ + struct phy_reg { + u16 reg; + u16 val; +@@ -1004,12 +1013,8 @@ static void rtl8125a_2_hw_phy_config(str + phy_write_paged(phydev, 0xac5, 0x16, 0x01ff); + phy_modify_paged(phydev, 0xac8, 0x15, 0x00f0, 0x0030); + +- phy_write(phydev, 0x1f, 0x0b87); +- phy_write(phydev, 0x16, 0x80a2); +- phy_write(phydev, 0x17, 0x0153); +- phy_write(phydev, 0x16, 0x809c); +- phy_write(phydev, 0x17, 0x0153); +- phy_write(phydev, 0x1f, 0x0000); ++ rtl8125_phy_param(phydev, 0x80a2, 0xffff, 0x0153); ++ rtl8125_phy_param(phydev, 0x809c, 0xffff, 0x0153); + + phy_write(phydev, 0x1f, 0x0a43); + phy_write(phydev, 0x13, 0x81B3); +@@ -1061,14 +1066,9 @@ static void rtl8125b_hw_phy_config(struc + phy_modify_paged(phydev, 0xac4, 0x13, 0x00f0, 0x0090); + phy_modify_paged(phydev, 0xad3, 0x10, 0x0003, 0x0001); + +- phy_write(phydev, 0x1f, 0x0b87); +- phy_write(phydev, 0x16, 0x80f5); +- phy_write(phydev, 0x17, 0x760e); +- phy_write(phydev, 0x16, 0x8107); +- phy_write(phydev, 0x17, 0x360e); +- phy_write(phydev, 0x16, 0x8551); +- phy_modify(phydev, 0x17, 0xff00, 0x0800); +- phy_write(phydev, 0x1f, 0x0000); ++ rtl8125_phy_param(phydev, 0x80f5, 0xffff, 0x760e); ++ rtl8125_phy_param(phydev, 0x8107, 0xffff, 0x360e); ++ rtl8125_phy_param(phydev, 0x8551, 0xff00, 0x0800); + + phy_modify_paged(phydev, 0xbf0, 0x10, 0xe000, 0xa000); + phy_modify_paged(phydev, 0xbf4, 0x13, 0x0f00, 0x0300); +@@ -1110,12 +1110,8 @@ static void rtl8125bp_hw_phy_config(stru + + r8168g_phy_param(phydev, 0x8010, 0x0800, 0x0000); + +- phy_write(phydev, 0x1f, 0x0b87); +- phy_write(phydev, 0x16, 0x8088); +- phy_modify(phydev, 0x17, 0xff00, 0x9000); +- phy_write(phydev, 0x16, 0x808f); +- phy_modify(phydev, 0x17, 0xff00, 0x9000); +- phy_write(phydev, 0x1f, 0x0000); ++ rtl8125_phy_param(phydev, 0x8088, 0xff00, 0x9000); ++ rtl8125_phy_param(phydev, 0x808f, 0xff00, 0x9000); + + r8168g_phy_param(phydev, 0x8174, 0x2000, 0x1800); + diff --git a/target/linux/generic/backport-6.6/780-59-v6.16-r8169-refactor-chip-version-detection.patch b/target/linux/generic/backport-6.6/780-59-v6.16-r8169-refactor-chip-version-detection.patch new file mode 100644 index 00000000000..7ffff5dc9be --- /dev/null +++ b/target/linux/generic/backport-6.6/780-59-v6.16-r8169-refactor-chip-version-detection.patch @@ -0,0 +1,401 @@ +From 2b065c098c37a3ed28df7c3be59dca61b9da8402 Mon Sep 17 00:00:00 2001 +From: Heiner Kallweit +Date: Tue, 15 Apr 2025 21:29:34 +0200 +Subject: [PATCH] r8169: refactor chip version detection + +Refactor chip version detection and merge both configuration tables. +Apart from reducing the code by a third, this paves the way for +merging chip version handling if only difference is the firmware. + +Signed-off-by: Heiner Kallweit +Reviewed-by: Michal Swiatkowski +Link: https://patch.msgid.link/1fea533a-dd5a-4198-a9e2-895e11083947@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/realtek/r8169_main.c | 325 +++++++++------------- + 1 file changed, 128 insertions(+), 197 deletions(-) + +--- a/drivers/net/ethernet/realtek/r8169_main.c ++++ b/drivers/net/ethernet/realtek/r8169_main.c +@@ -91,61 +91,114 @@ + #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) + #define JUMBO_16K (SZ_16K - VLAN_ETH_HLEN - ETH_FCS_LEN) + +-static const struct { ++static const struct rtl_chip_info { ++ u16 mask; ++ u16 val; ++ enum mac_version mac_version; + const char *name; + const char *fw_name; + } rtl_chip_infos[] = { +- /* PCI devices. */ +- [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, +- [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, +- [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, +- [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, +- [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, +- /* PCI-E devices. */ +- [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, +- [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, +- [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, +- [RTL_GIGA_MAC_VER_10] = {"RTL8101e/RTL8100e" }, +- [RTL_GIGA_MAC_VER_14] = {"RTL8401" }, +- [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, +- [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, +- [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, +- [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, +- [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, +- [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, +- [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, +- [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, +- [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, +- [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, +- [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, +- [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, +- [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, +- [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, +- [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, +- [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, +- [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, +- [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, +- [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, +- [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, +- [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, +- [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, +- [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, +- [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, +- [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, +- [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, +- [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, +- [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, +- [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, +- [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3}, +- [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117", }, +- [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3}, +- /* reserve 62 for CFG_METHOD_4 in the vendor driver */ +- [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2}, +- [RTL_GIGA_MAC_VER_64] = {"RTL8125D", FIRMWARE_8125D_1}, +- [RTL_GIGA_MAC_VER_65] = {"RTL8125D", FIRMWARE_8125D_2}, +- [RTL_GIGA_MAC_VER_66] = {"RTL8125BP", FIRMWARE_8125BP_2}, +- [RTL_GIGA_MAC_VER_70] = {"RTL8126A", FIRMWARE_8126A_2}, +- [RTL_GIGA_MAC_VER_71] = {"RTL8126A", FIRMWARE_8126A_3}, ++ /* 8126A family. */ ++ { 0x7cf, 0x64a, RTL_GIGA_MAC_VER_71, "RTL8126A", FIRMWARE_8126A_3 }, ++ { 0x7cf, 0x649, RTL_GIGA_MAC_VER_70, "RTL8126A", FIRMWARE_8126A_2 }, ++ ++ /* 8125BP family. */ ++ { 0x7cf, 0x681, RTL_GIGA_MAC_VER_66, "RTL8125BP", FIRMWARE_8125BP_2 }, ++ ++ /* 8125D family. */ ++ { 0x7cf, 0x689, RTL_GIGA_MAC_VER_65, "RTL8125D", FIRMWARE_8125D_2 }, ++ { 0x7cf, 0x688, RTL_GIGA_MAC_VER_64, "RTL8125D", FIRMWARE_8125D_1 }, ++ ++ /* 8125B family. */ ++ { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63, "RTL8125B", FIRMWARE_8125B_2 }, ++ ++ /* 8125A family. */ ++ { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61, "RTL8125A", FIRMWARE_8125A_3 }, ++ ++ /* RTL8117 */ ++ { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53, "RTL8168fp/RTL8117" }, ++ { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52, "RTL8168fp/RTL8117", ++ FIRMWARE_8168FP_3 }, ++ ++ /* 8168EP family. */ ++ { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51, "RTL8168ep/8111ep" }, ++ ++ /* 8168H family. */ ++ { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46, "RTL8168h/8111h", ++ FIRMWARE_8168H_2 }, ++ /* Realtek calls it RTL8168M, but it's handled like RTL8168H */ ++ { 0x7cf, 0x6c0, RTL_GIGA_MAC_VER_46, "RTL8168M", FIRMWARE_8168H_2 }, ++ ++ /* 8168G family. */ ++ { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44, "RTL8411b", FIRMWARE_8411_2 }, ++ { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42, "RTL8168gu/8111gu", ++ FIRMWARE_8168G_3 }, ++ { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40, "RTL8168g/8111g", ++ FIRMWARE_8168G_2 }, ++ ++ /* 8168F family. */ ++ { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38, "RTL8411", FIRMWARE_8411_1 }, ++ { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36, "RTL8168f/8111f", ++ FIRMWARE_8168F_2 }, ++ { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35, "RTL8168f/8111f", ++ FIRMWARE_8168F_1 }, ++ ++ /* 8168E family. */ ++ { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34, "RTL8168evl/8111evl", ++ FIRMWARE_8168E_3 }, ++ { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32, "RTL8168e/8111e", ++ FIRMWARE_8168E_1 }, ++ { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33, "RTL8168e/8111e", ++ FIRMWARE_8168E_2 }, ++ ++ /* 8168D family. */ ++ { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25, "RTL8168d/8111d", ++ FIRMWARE_8168D_1 }, ++ { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26, "RTL8168d/8111d", ++ FIRMWARE_8168D_2 }, ++ ++ /* 8168DP family. */ ++ { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28, "RTL8168dp/8111dp" }, ++ { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31, "RTL8168dp/8111dp" }, ++ ++ /* 8168C family. */ ++ { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23, "RTL8168cp/8111cp" }, ++ { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18, "RTL8168cp/8111cp" }, ++ { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24, "RTL8168cp/8111cp" }, ++ { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19, "RTL8168c/8111c" }, ++ { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20, "RTL8168c/8111c" }, ++ { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21, "RTL8168c/8111c" }, ++ { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22, "RTL8168c/8111c" }, ++ ++ /* 8168B family. */ ++ { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17, "RTL8168b/8111b" }, ++ /* This one is very old and rare, support has been removed. ++ * { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11, "RTL8168b/8111b" }, ++ */ ++ ++ /* 8101 family. */ ++ { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39, "RTL8106e", FIRMWARE_8106E_1 }, ++ { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37, "RTL8402", FIRMWARE_8402_1 }, ++ { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29, "RTL8105e", FIRMWARE_8105E_1 }, ++ { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30, "RTL8105e", FIRMWARE_8105E_1 }, ++ { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08, "RTL8102e" }, ++ { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08, "RTL8102e" }, ++ { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07, "RTL8102e" }, ++ { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07, "RTL8102e" }, ++ { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14, "RTL8401" }, ++ { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09, "RTL8102e/RTL8103e" }, ++ { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09, "RTL8102e/RTL8103e" }, ++ { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10, "RTL8101e/RTL8100e" }, ++ ++ /* 8110 family. */ ++ { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06, "RTL8169sc/8110sc" }, ++ { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05, "RTL8169sc/8110sc" }, ++ { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04, "RTL8169sb/8110sb" }, ++ { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03, "RTL8110s" }, ++ { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02, "RTL8169s" }, ++ ++ /* Catch-all */ ++ { 0x000, 0x000, RTL_GIGA_MAC_NONE } + }; + + static const struct pci_device_id rtl8169_pci_tbl[] = { +@@ -2267,151 +2320,30 @@ static const struct ethtool_ops rtl8169_ + .get_eth_ctrl_stats = rtl8169_get_eth_ctrl_stats, + }; + +-static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii) ++static const struct rtl_chip_info *rtl8169_get_chip_version(u16 xid, bool gmii) + { +- /* +- * The driver currently handles the 8168Bf and the 8168Be identically +- * but they can be identified more specifically through the test below +- * if needed: +- * +- * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be +- * +- * Same thing for the 8101Eb and the 8101Ec: +- * +- * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec +- */ +- static const struct rtl_mac_info { +- u16 mask; +- u16 val; +- enum mac_version ver; +- } mac_info[] = { +- /* 8126A family. */ +- { 0x7cf, 0x64a, RTL_GIGA_MAC_VER_71 }, +- { 0x7cf, 0x649, RTL_GIGA_MAC_VER_70 }, +- +- /* 8125BP family. */ +- { 0x7cf, 0x681, RTL_GIGA_MAC_VER_66 }, +- +- /* 8125D family. */ +- { 0x7cf, 0x689, RTL_GIGA_MAC_VER_65 }, +- { 0x7cf, 0x688, RTL_GIGA_MAC_VER_64 }, +- +- /* 8125B family. */ +- { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 }, +- +- /* 8125A family. */ +- { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61 }, +- /* It seems only XID 609 made it to the mass market. +- * { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, +- * { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, +- */ +- +- /* RTL8117 */ +- { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 }, +- { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, +- +- /* 8168EP family. */ +- { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, +- /* It seems this chip version never made it to +- * the wild. Let's disable detection. +- * { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, +- * { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, +- */ +- +- /* 8168H family. */ +- { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, +- /* It seems this chip version never made it to +- * the wild. Let's disable detection. +- * { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, +- */ +- /* Realtek calls it RTL8168M, but it's handled like RTL8168H */ +- { 0x7cf, 0x6c0, RTL_GIGA_MAC_VER_46 }, +- +- /* 8168G family. */ +- { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, +- { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, +- /* It seems this chip version never made it to +- * the wild. Let's disable detection. +- * { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, +- */ +- { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, +- +- /* 8168F family. */ +- { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, +- { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, +- { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, +- +- /* 8168E family. */ +- { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, +- { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, +- { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, +- +- /* 8168D family. */ +- { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, +- { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, +- +- /* 8168DP family. */ +- /* It seems this early RTL8168dp version never made it to +- * the wild. Support has been removed. +- * { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, +- */ +- { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, +- { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, +- +- /* 8168C family. */ +- { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, +- { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, +- { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, +- { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, +- { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, +- { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, +- { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, +- +- /* 8168B family. */ +- { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, +- /* This one is very old and rare, support has been removed. +- * { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, +- */ +- +- /* 8101 family. */ +- { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, +- { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, +- { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, +- { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, +- { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, +- { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, +- { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, +- { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, +- { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 }, +- { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, +- { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, +- { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10 }, +- +- /* 8110 family. */ +- { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, +- { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, +- { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, +- { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, +- { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, +- +- /* Catch-all */ +- { 0x000, 0x000, RTL_GIGA_MAC_NONE } ++ /* Chips combining a 1Gbps MAC with a 100Mbps PHY */ ++ static const struct rtl_chip_info rtl8106eus_info = { ++ .mac_version = RTL_GIGA_MAC_VER_43, ++ .name = "RTL8106eus", ++ .fw_name = FIRMWARE_8106E_2, + }; +- const struct rtl_mac_info *p = mac_info; +- enum mac_version ver; ++ static const struct rtl_chip_info rtl8107e_info = { ++ .mac_version = RTL_GIGA_MAC_VER_48, ++ .name = "RTL8107e", ++ .fw_name = FIRMWARE_8107E_2, ++ }; ++ const struct rtl_chip_info *p = rtl_chip_infos; + + while ((xid & p->mask) != p->val) + p++; +- ver = p->ver; + +- if (ver != RTL_GIGA_MAC_NONE && !gmii) { +- if (ver == RTL_GIGA_MAC_VER_42) +- ver = RTL_GIGA_MAC_VER_43; +- else if (ver == RTL_GIGA_MAC_VER_46) +- ver = RTL_GIGA_MAC_VER_48; +- } ++ if (p->mac_version == RTL_GIGA_MAC_VER_42 && !gmii) ++ return &rtl8106eus_info; ++ if (p->mac_version == RTL_GIGA_MAC_VER_46 && !gmii) ++ return &rtl8107e_info; + +- return ver; ++ return p; + } + + static void rtl_release_firmware(struct rtl8169_private *tp) +@@ -5448,9 +5380,9 @@ static bool rtl_aspm_is_safe(struct rtl8 + + static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) + { ++ const struct rtl_chip_info *chip; + struct rtl8169_private *tp; + int jumbo_max, region, rc; +- enum mac_version chipset; + struct net_device *dev; + u32 txconfig; + u16 xid; +@@ -5501,12 +5433,13 @@ static int rtl_init_one(struct pci_dev * + xid = (txconfig >> 20) & 0xfcf; + + /* Identify chip attached to board */ +- chipset = rtl8169_get_mac_version(xid, tp->supports_gmii); +- if (chipset == RTL_GIGA_MAC_NONE) ++ chip = rtl8169_get_chip_version(xid, tp->supports_gmii); ++ if (chip->mac_version == RTL_GIGA_MAC_NONE) + return dev_err_probe(&pdev->dev, -ENODEV, + "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n", + xid); +- tp->mac_version = chipset; ++ tp->mac_version = chip->mac_version; ++ tp->fw_name = chip->fw_name; + + /* Disable ASPM L1 as that cause random device stop working + * problems as well as full system hangs for some PCIe devices users. +@@ -5610,8 +5543,6 @@ static int rtl_init_one(struct pci_dev * + + rtl_set_irq_mask(tp); + +- tp->fw_name = rtl_chip_infos[chipset].fw_name; +- + tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), + &tp->counters_phys_addr, + GFP_KERNEL); +@@ -5636,7 +5567,7 @@ static int rtl_init_one(struct pci_dev * + } + + netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n", +- rtl_chip_infos[chipset].name, dev->dev_addr, xid, tp->irq); ++ chip->name, dev->dev_addr, xid, tp->irq); + + if (jumbo_max) + netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n", diff --git a/target/linux/generic/backport-6.6/780-60-v6.16-r8169-add-RTL_GIGA_MAC_VER_LAST-to-facilitate-adding.patch b/target/linux/generic/backport-6.6/780-60-v6.16-r8169-add-RTL_GIGA_MAC_VER_LAST-to-facilitate-adding.patch new file mode 100644 index 00000000000..b46d331a3c8 --- /dev/null +++ b/target/linux/generic/backport-6.6/780-60-v6.16-r8169-add-RTL_GIGA_MAC_VER_LAST-to-facilitate-adding.patch @@ -0,0 +1,159 @@ +From fe733618b27a8c033f0d246c2efff56fca322656 Mon Sep 17 00:00:00 2001 +From: Heiner Kallweit +Date: Tue, 15 Apr 2025 21:39:23 +0200 +Subject: [PATCH] r8169: add RTL_GIGA_MAC_VER_LAST to facilitate adding support + for new chip versions + +Add a new mac_version enum value RTL_GIGA_MAC_VER_LAST. Benefit is that +when adding support for a new chip version we have to touch less code, +except something changes fundamentally. + +Signed-off-by: Heiner Kallweit +Reviewed-by: Simon Horman +Link: https://patch.msgid.link/06991f47-2aec-4aa2-8918-2c6e79332303@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/realtek/r8169.h | 3 ++- + drivers/net/ethernet/realtek/r8169_main.c | 28 +++++++++++------------ + 2 files changed, 16 insertions(+), 15 deletions(-) + +--- a/drivers/net/ethernet/realtek/r8169.h ++++ b/drivers/net/ethernet/realtek/r8169.h +@@ -73,7 +73,8 @@ enum mac_version { + RTL_GIGA_MAC_VER_66, + RTL_GIGA_MAC_VER_70, + RTL_GIGA_MAC_VER_71, +- RTL_GIGA_MAC_NONE ++ RTL_GIGA_MAC_NONE, ++ RTL_GIGA_MAC_VER_LAST = RTL_GIGA_MAC_NONE - 1 + }; + + struct rtl8169_private; +--- a/drivers/net/ethernet/realtek/r8169_main.c ++++ b/drivers/net/ethernet/realtek/r8169_main.c +@@ -1290,7 +1290,7 @@ static void rtl_writephy(struct rtl8169_ + case RTL_GIGA_MAC_VER_31: + r8168dp_2_mdio_write(tp, location, val); + break; +- case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_71: ++ case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST: + r8168g_mdio_write(tp, location, val); + break; + default: +@@ -1305,7 +1305,7 @@ static int rtl_readphy(struct rtl8169_pr + case RTL_GIGA_MAC_VER_28: + case RTL_GIGA_MAC_VER_31: + return r8168dp_2_mdio_read(tp, location); +- case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_71: ++ case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST: + return r8168g_mdio_read(tp, location); + default: + return r8169_mdio_read(tp, location); +@@ -1657,7 +1657,7 @@ static void __rtl8169_set_wol(struct rtl + break; + case RTL_GIGA_MAC_VER_34: + case RTL_GIGA_MAC_VER_37: +- case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_71: ++ case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_LAST: + r8169_mod_reg8_cond(tp, Config2, PME_SIGNAL, wolopts); + break; + default: +@@ -2130,7 +2130,7 @@ static void rtl_set_eee_txidle_timer(str + tp->tx_lpi_timer = timer_val; + r8168_mac_ocp_write(tp, 0xe048, timer_val); + break; +- case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_71: ++ case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: + tp->tx_lpi_timer = timer_val; + RTL_W16(tp, EEE_TXIDLE_TIMER_8125, timer_val); + break; +@@ -2495,7 +2495,7 @@ static void rtl_init_rxcfg(struct rtl816 + case RTL_GIGA_MAC_VER_61: + RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); + break; +- case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_71: ++ case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_LAST: + RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST | + RX_PAUSE_SLOT_ON); + break; +@@ -2627,7 +2627,7 @@ static void rtl_wait_txrx_fifo_empty(str + case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61: + rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); + break; +- case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_71: ++ case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_LAST: + RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); + rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); + rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42); +@@ -2902,7 +2902,7 @@ static void rtl_enable_exit_l1(struct rt + case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38: + rtl_eri_set_bits(tp, 0xd4, 0x0c00); + break; +- case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_71: ++ case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST: + r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80); + break; + default: +@@ -2916,7 +2916,7 @@ static void rtl_disable_exit_l1(struct r + case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: + rtl_eri_clear_bits(tp, 0xd4, 0x1f00); + break; +- case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_71: ++ case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST: + r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0); + break; + default: +@@ -2954,7 +2954,7 @@ static void rtl_hw_aspm_clkreq_enable(st + + switch (tp->mac_version) { + case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: +- case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_71: ++ case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: + /* reset ephy tx/rx disable timer */ + r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0); + /* chip can trigger L1.2 */ +@@ -2966,7 +2966,7 @@ static void rtl_hw_aspm_clkreq_enable(st + } else { + switch (tp->mac_version) { + case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: +- case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_71: ++ case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: + r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0); + break; + default: +@@ -4098,7 +4098,7 @@ static void rtl8169_cleanup(struct rtl81 + RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); + rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); + break; +- case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_71: ++ case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST: + rtl_enable_rxdvgate(tp); + fsleep(2000); + break; +@@ -4255,7 +4255,7 @@ static unsigned int rtl_quirk_packet_pad + + switch (tp->mac_version) { + case RTL_GIGA_MAC_VER_34: +- case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_71: ++ case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: + padto = max_t(unsigned int, padto, ETH_ZLEN); + break; + default: +@@ -5310,7 +5310,7 @@ static void rtl_hw_initialize(struct rtl + case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: + rtl_hw_init_8168g(tp); + break; +- case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_71: ++ case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: + rtl_hw_init_8125(tp); + break; + default: +@@ -5335,7 +5335,7 @@ static int rtl_jumbo_max(struct rtl8169_ + case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: + return JUMBO_6K; + /* RTL8125/8126 */ +- case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_71: ++ case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: + return JUMBO_16K; + default: + return JUMBO_9K; diff --git a/target/linux/generic/backport-6.6/780-61-v6.16-r8169-use-pci_prepare_to_sleep-in-rtl_shutdown.patch b/target/linux/generic/backport-6.6/780-61-v6.16-r8169-use-pci_prepare_to_sleep-in-rtl_shutdown.patch new file mode 100644 index 00000000000..21fdca10315 --- /dev/null +++ b/target/linux/generic/backport-6.6/780-61-v6.16-r8169-use-pci_prepare_to_sleep-in-rtl_shutdown.patch @@ -0,0 +1,37 @@ +From b7ed5d5a78fccee96cf8919ac2c7a064c2f4c45b Mon Sep 17 00:00:00 2001 +From: Heiner Kallweit +Date: Mon, 21 Apr 2025 11:25:18 +0200 +Subject: [PATCH] r8169: use pci_prepare_to_sleep in rtl_shutdown + +Use pci_prepare_to_sleep() like PCI core does in pci_pm_suspend_noirq. +This aligns setting a low-power mode during shutdown with the handling +of the transition to system suspend. Also the transition to runtime +suspend uses pci_target_state() instead of setting D3hot unconditionally. + +Note: pci_prepare_to_sleep() uses device_may_wakeup() to check whether + device may generate wakeup events. So we don't lose anything by + not passing tp->saved_wolopts any longer. + +Signed-off-by: Heiner Kallweit +Reviewed-by: Jacob Keller +Link: https://patch.msgid.link/f573fdbd-ba6d-41c1-b68f-311d3c88db2c@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/realtek/r8169_main.c | 6 ++---- + 1 file changed, 2 insertions(+), 4 deletions(-) + +--- a/drivers/net/ethernet/realtek/r8169_main.c ++++ b/drivers/net/ethernet/realtek/r8169_main.c +@@ -5047,10 +5047,8 @@ static void rtl_shutdown(struct pci_dev + /* Restore original MAC address */ + rtl_rar_set(tp, tp->dev->perm_addr); + +- if (system_state == SYSTEM_POWER_OFF && !tp->dash_enabled) { +- pci_wake_from_d3(pdev, tp->saved_wolopts); +- pci_set_power_state(pdev, PCI_D3hot); +- } ++ if (system_state == SYSTEM_POWER_OFF && !tp->dash_enabled) ++ pci_prepare_to_sleep(pdev); + } + + static void rtl_remove_one(struct pci_dev *pdev) diff --git a/target/linux/generic/backport-6.6/780-62-v6.16-r8169-merge-chip-versions-70-and-71-RTL8126A.patch b/target/linux/generic/backport-6.6/780-62-v6.16-r8169-merge-chip-versions-70-and-71-RTL8126A.patch new file mode 100644 index 00000000000..08f7d4f90ad --- /dev/null +++ b/target/linux/generic/backport-6.6/780-62-v6.16-r8169-merge-chip-versions-70-and-71-RTL8126A.patch @@ -0,0 +1,106 @@ +From 4dec0702b8627c364a0e1f2c5b249e06709a1c24 Mon Sep 17 00:00:00 2001 +From: Heiner Kallweit +Date: Fri, 18 Apr 2025 11:23:45 +0200 +Subject: [PATCH] r8169: merge chip versions 70 and 71 (RTL8126A) + +Handling of both chip versions is the same, only difference is +the firmware. So we can merge handling of both chip versions. + +Signed-off-by: Heiner Kallweit +Reviewed-by: Simon Horman +Link: https://patch.msgid.link/97d7ae79-d021-4b6b-b424-89e5e305b029@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/realtek/r8169.h | 1 - + drivers/net/ethernet/realtek/r8169_main.c | 15 ++++----------- + drivers/net/ethernet/realtek/r8169_phy_config.c | 1 - + 3 files changed, 4 insertions(+), 13 deletions(-) + +--- a/drivers/net/ethernet/realtek/r8169.h ++++ b/drivers/net/ethernet/realtek/r8169.h +@@ -72,7 +72,6 @@ enum mac_version { + RTL_GIGA_MAC_VER_65, + RTL_GIGA_MAC_VER_66, + RTL_GIGA_MAC_VER_70, +- RTL_GIGA_MAC_VER_71, + RTL_GIGA_MAC_NONE, + RTL_GIGA_MAC_VER_LAST = RTL_GIGA_MAC_NONE - 1 + }; +--- a/drivers/net/ethernet/realtek/r8169_main.c ++++ b/drivers/net/ethernet/realtek/r8169_main.c +@@ -99,7 +99,7 @@ static const struct rtl_chip_info { + const char *fw_name; + } rtl_chip_infos[] = { + /* 8126A family. */ +- { 0x7cf, 0x64a, RTL_GIGA_MAC_VER_71, "RTL8126A", FIRMWARE_8126A_3 }, ++ { 0x7cf, 0x64a, RTL_GIGA_MAC_VER_70, "RTL8126A", FIRMWARE_8126A_3 }, + { 0x7cf, 0x649, RTL_GIGA_MAC_VER_70, "RTL8126A", FIRMWARE_8126A_2 }, + + /* 8125BP family. */ +@@ -2943,7 +2943,6 @@ static void rtl_hw_aspm_clkreq_enable(st + rtl_mod_config5(tp, 0, ASPM_en); + switch (tp->mac_version) { + case RTL_GIGA_MAC_VER_70: +- case RTL_GIGA_MAC_VER_71: + val8 = RTL_R8(tp, INT_CFG0_8125) | INT_CFG0_CLKREQEN; + RTL_W8(tp, INT_CFG0_8125, val8); + break; +@@ -2975,7 +2974,6 @@ static void rtl_hw_aspm_clkreq_enable(st + + switch (tp->mac_version) { + case RTL_GIGA_MAC_VER_70: +- case RTL_GIGA_MAC_VER_71: + val8 = RTL_R8(tp, INT_CFG0_8125) & ~INT_CFG0_CLKREQEN; + RTL_W8(tp, INT_CFG0_8125, val8); + break; +@@ -3695,12 +3693,10 @@ static void rtl_hw_start_8125_common(str + /* disable new tx descriptor format */ + r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); + +- if (tp->mac_version == RTL_GIGA_MAC_VER_70 || +- tp->mac_version == RTL_GIGA_MAC_VER_71) ++ if (tp->mac_version == RTL_GIGA_MAC_VER_70) + RTL_W8(tp, 0xD8, RTL_R8(tp, 0xD8) & ~0x02); + +- if (tp->mac_version == RTL_GIGA_MAC_VER_70 || +- tp->mac_version == RTL_GIGA_MAC_VER_71) ++ if (tp->mac_version == RTL_GIGA_MAC_VER_70) + r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); + else if (tp->mac_version == RTL_GIGA_MAC_VER_63) + r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); +@@ -3718,8 +3714,7 @@ static void rtl_hw_start_8125_common(str + r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); + r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); + r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); +- if (tp->mac_version == RTL_GIGA_MAC_VER_70 || +- tp->mac_version == RTL_GIGA_MAC_VER_71) ++ if (tp->mac_version == RTL_GIGA_MAC_VER_70) + r8168_mac_ocp_modify(tp, 0xea1c, 0x0300, 0x0000); + else + r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); +@@ -3842,7 +3837,6 @@ static void rtl_hw_config(struct rtl8169 + [RTL_GIGA_MAC_VER_65] = rtl_hw_start_8125d, + [RTL_GIGA_MAC_VER_66] = rtl_hw_start_8125d, + [RTL_GIGA_MAC_VER_70] = rtl_hw_start_8126a, +- [RTL_GIGA_MAC_VER_71] = rtl_hw_start_8126a, + }; + + if (hw_configs[tp->mac_version]) +@@ -3866,7 +3860,6 @@ static void rtl_hw_start_8125(struct rtl + break; + case RTL_GIGA_MAC_VER_63: + case RTL_GIGA_MAC_VER_70: +- case RTL_GIGA_MAC_VER_71: + for (i = 0xa00; i < 0xa80; i += 4) + RTL_W32(tp, i, 0); + RTL_W16(tp, INT_CFG1_8125, 0x0000); +--- a/drivers/net/ethernet/realtek/r8169_phy_config.c ++++ b/drivers/net/ethernet/realtek/r8169_phy_config.c +@@ -1183,7 +1183,6 @@ void r8169_hw_phy_config(struct rtl8169_ + [RTL_GIGA_MAC_VER_65] = rtl8125d_hw_phy_config, + [RTL_GIGA_MAC_VER_66] = rtl8125bp_hw_phy_config, + [RTL_GIGA_MAC_VER_70] = rtl8126a_hw_phy_config, +- [RTL_GIGA_MAC_VER_71] = rtl8126a_hw_phy_config, + }; + + if (phy_configs[ver]) diff --git a/target/linux/generic/backport-6.6/780-63-v6.16-r8169-merge-chip-versions-64-and-65-RTL8125D.patch b/target/linux/generic/backport-6.6/780-63-v6.16-r8169-merge-chip-versions-64-and-65-RTL8125D.patch new file mode 100644 index 00000000000..5b29ccd0a10 --- /dev/null +++ b/target/linux/generic/backport-6.6/780-63-v6.16-r8169-merge-chip-versions-64-and-65-RTL8125D.patch @@ -0,0 +1,65 @@ +From f372ef6ed5a6b0401c884561d4bba1843e54d46a Mon Sep 17 00:00:00 2001 +From: Heiner Kallweit +Date: Fri, 18 Apr 2025 11:24:30 +0200 +Subject: [PATCH] r8169: merge chip versions 64 and 65 (RTL8125D) + +Handling of both chip versions is the same, only difference is +the firmware. So we can merge handling of both chip versions. + +Signed-off-by: Heiner Kallweit +Reviewed-by: Simon Horman +Link: https://patch.msgid.link/0baad123-c679-4154-923f-fdc12783e900@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/realtek/r8169.h | 1 - + drivers/net/ethernet/realtek/r8169_main.c | 4 +--- + drivers/net/ethernet/realtek/r8169_phy_config.c | 1 - + 3 files changed, 1 insertion(+), 5 deletions(-) + +--- a/drivers/net/ethernet/realtek/r8169.h ++++ b/drivers/net/ethernet/realtek/r8169.h +@@ -69,7 +69,6 @@ enum mac_version { + RTL_GIGA_MAC_VER_61, + RTL_GIGA_MAC_VER_63, + RTL_GIGA_MAC_VER_64, +- RTL_GIGA_MAC_VER_65, + RTL_GIGA_MAC_VER_66, + RTL_GIGA_MAC_VER_70, + RTL_GIGA_MAC_NONE, +--- a/drivers/net/ethernet/realtek/r8169_main.c ++++ b/drivers/net/ethernet/realtek/r8169_main.c +@@ -106,7 +106,7 @@ static const struct rtl_chip_info { + { 0x7cf, 0x681, RTL_GIGA_MAC_VER_66, "RTL8125BP", FIRMWARE_8125BP_2 }, + + /* 8125D family. */ +- { 0x7cf, 0x689, RTL_GIGA_MAC_VER_65, "RTL8125D", FIRMWARE_8125D_2 }, ++ { 0x7cf, 0x689, RTL_GIGA_MAC_VER_64, "RTL8125D", FIRMWARE_8125D_2 }, + { 0x7cf, 0x688, RTL_GIGA_MAC_VER_64, "RTL8125D", FIRMWARE_8125D_1 }, + + /* 8125B family. */ +@@ -3834,7 +3834,6 @@ static void rtl_hw_config(struct rtl8169 + [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2, + [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, + [RTL_GIGA_MAC_VER_64] = rtl_hw_start_8125d, +- [RTL_GIGA_MAC_VER_65] = rtl_hw_start_8125d, + [RTL_GIGA_MAC_VER_66] = rtl_hw_start_8125d, + [RTL_GIGA_MAC_VER_70] = rtl_hw_start_8126a, + }; +@@ -3853,7 +3852,6 @@ static void rtl_hw_start_8125(struct rtl + switch (tp->mac_version) { + case RTL_GIGA_MAC_VER_61: + case RTL_GIGA_MAC_VER_64: +- case RTL_GIGA_MAC_VER_65: + case RTL_GIGA_MAC_VER_66: + for (i = 0xa00; i < 0xb00; i += 4) + RTL_W32(tp, i, 0); +--- a/drivers/net/ethernet/realtek/r8169_phy_config.c ++++ b/drivers/net/ethernet/realtek/r8169_phy_config.c +@@ -1180,7 +1180,6 @@ void r8169_hw_phy_config(struct rtl8169_ + [RTL_GIGA_MAC_VER_61] = rtl8125a_2_hw_phy_config, + [RTL_GIGA_MAC_VER_63] = rtl8125b_hw_phy_config, + [RTL_GIGA_MAC_VER_64] = rtl8125d_hw_phy_config, +- [RTL_GIGA_MAC_VER_65] = rtl8125d_hw_phy_config, + [RTL_GIGA_MAC_VER_66] = rtl8125bp_hw_phy_config, + [RTL_GIGA_MAC_VER_70] = rtl8126a_hw_phy_config, + }; diff --git a/target/linux/generic/backport-6.6/780-64-v6.16-r8169-merge-chip-versions-52-and-53-RTL8117.patch b/target/linux/generic/backport-6.6/780-64-v6.16-r8169-merge-chip-versions-52-and-53-RTL8117.patch new file mode 100644 index 00000000000..a03eb9f208b --- /dev/null +++ b/target/linux/generic/backport-6.6/780-64-v6.16-r8169-merge-chip-versions-52-and-53-RTL8117.patch @@ -0,0 +1,113 @@ +From 4f51e7d370a04122fa78470b031d6487c52298b1 Mon Sep 17 00:00:00 2001 +From: Heiner Kallweit +Date: Fri, 18 Apr 2025 11:25:17 +0200 +Subject: [PATCH] r8169: merge chip versions 52 and 53 (RTL8117) + +Handling of both chip versions is the same, only difference is +the firmware. So we can merge handling of both chip versions. + +Signed-off-by: Heiner Kallweit +Reviewed-by: Simon Horman +Link: https://patch.msgid.link/ae866b71-c904-434e-befb-848c831e33ff@gmail.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/realtek/r8169.h | 1 - + drivers/net/ethernet/realtek/r8169_main.c | 17 +++++++---------- + drivers/net/ethernet/realtek/r8169_phy_config.c | 1 - + 3 files changed, 7 insertions(+), 12 deletions(-) + +--- a/drivers/net/ethernet/realtek/r8169.h ++++ b/drivers/net/ethernet/realtek/r8169.h +@@ -64,7 +64,6 @@ enum mac_version { + /* support for RTL_GIGA_MAC_VER_50 has been removed */ + RTL_GIGA_MAC_VER_51, + RTL_GIGA_MAC_VER_52, +- RTL_GIGA_MAC_VER_53, + /* support for RTL_GIGA_MAC_VER_60 has been removed */ + RTL_GIGA_MAC_VER_61, + RTL_GIGA_MAC_VER_63, +--- a/drivers/net/ethernet/realtek/r8169_main.c ++++ b/drivers/net/ethernet/realtek/r8169_main.c +@@ -116,7 +116,7 @@ static const struct rtl_chip_info { + { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61, "RTL8125A", FIRMWARE_8125A_3 }, + + /* RTL8117 */ +- { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53, "RTL8168fp/RTL8117" }, ++ { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_52, "RTL8168fp/RTL8117" }, + { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52, "RTL8168fp/RTL8117", + FIRMWARE_8168FP_3 }, + +@@ -831,7 +831,7 @@ static bool rtl_is_8168evl_up(struct rtl + { + return tp->mac_version >= RTL_GIGA_MAC_VER_34 && + tp->mac_version != RTL_GIGA_MAC_VER_39 && +- tp->mac_version <= RTL_GIGA_MAC_VER_53; ++ tp->mac_version <= RTL_GIGA_MAC_VER_52; + } + + static bool rtl_supports_eee(struct rtl8169_private *tp) +@@ -999,9 +999,7 @@ void r8169_get_led_name(struct rtl8169_p + static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type) + { + /* based on RTL8168FP_OOBMAC_BASE in vendor driver */ +- if (type == ERIAR_OOB && +- (tp->mac_version == RTL_GIGA_MAC_VER_52 || +- tp->mac_version == RTL_GIGA_MAC_VER_53)) ++ if (type == ERIAR_OOB && tp->mac_version == RTL_GIGA_MAC_VER_52) + *cmd |= 0xf70 << 18; + } + +@@ -1501,7 +1499,7 @@ static enum rtl_dash_type rtl_get_dash_t + case RTL_GIGA_MAC_VER_28: + case RTL_GIGA_MAC_VER_31: + return RTL_DASH_DP; +- case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: ++ case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_52: + return RTL_DASH_EP; + case RTL_GIGA_MAC_VER_66: + return RTL_DASH_25_BP; +@@ -2489,7 +2487,7 @@ static void rtl_init_rxcfg(struct rtl816 + case RTL_GIGA_MAC_VER_38: + RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); + break; +- case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: ++ case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52: + RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); + break; + case RTL_GIGA_MAC_VER_61: +@@ -2620,7 +2618,7 @@ DECLARE_RTL_COND(rtl_rxtx_empty_cond_2) + static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp) + { + switch (tp->mac_version) { +- case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: ++ case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52: + rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42); + rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); + break; +@@ -3830,7 +3828,6 @@ static void rtl_hw_config(struct rtl8169 + [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, + [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, + [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, +- [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117, + [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2, + [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, + [RTL_GIGA_MAC_VER_64] = rtl_hw_start_8125d, +@@ -5293,7 +5290,7 @@ static void rtl_hw_init_8125(struct rtl8 + static void rtl_hw_initialize(struct rtl8169_private *tp) + { + switch (tp->mac_version) { +- case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: ++ case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_52: + rtl8168ep_stop_cmac(tp); + fallthrough; + case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: +--- a/drivers/net/ethernet/realtek/r8169_phy_config.c ++++ b/drivers/net/ethernet/realtek/r8169_phy_config.c +@@ -1176,7 +1176,6 @@ void r8169_hw_phy_config(struct rtl8169_ + [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config, + [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config, + [RTL_GIGA_MAC_VER_52] = rtl8117_hw_phy_config, +- [RTL_GIGA_MAC_VER_53] = rtl8117_hw_phy_config, + [RTL_GIGA_MAC_VER_61] = rtl8125a_2_hw_phy_config, + [RTL_GIGA_MAC_VER_63] = rtl8125b_hw_phy_config, + [RTL_GIGA_MAC_VER_64] = rtl8125d_hw_phy_config, diff --git a/target/linux/generic/backport-6.6/780-65-v6.16-r8169-add-support-for-RTL8127A.patch b/target/linux/generic/backport-6.6/780-65-v6.16-r8169-add-support-for-RTL8127A.patch new file mode 100644 index 00000000000..93f7bbc0cf2 --- /dev/null +++ b/target/linux/generic/backport-6.6/780-65-v6.16-r8169-add-support-for-RTL8127A.patch @@ -0,0 +1,323 @@ +From f24f7b2f3af9e008ded20f804d7829ee2efd43f2 Mon Sep 17 00:00:00 2001 +From: ChunHao Lin +Date: Thu, 15 May 2025 17:53:03 +0800 +Subject: [PATCH] r8169: add support for RTL8127A + +This adds support for 10Gbs chip RTL8127A. + +Signed-off-by: ChunHao Lin +Reviewed-by: Heiner Kallweit +Link: https://patch.msgid.link/20250515095303.3138-1-hau@realtek.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/realtek/r8169.h | 1 + + drivers/net/ethernet/realtek/r8169_main.c | 29 ++- + .../net/ethernet/realtek/r8169_phy_config.c | 166 ++++++++++++++++++ + 3 files changed, 193 insertions(+), 3 deletions(-) + +--- a/drivers/net/ethernet/realtek/r8169.h ++++ b/drivers/net/ethernet/realtek/r8169.h +@@ -70,6 +70,7 @@ enum mac_version { + RTL_GIGA_MAC_VER_64, + RTL_GIGA_MAC_VER_66, + RTL_GIGA_MAC_VER_70, ++ RTL_GIGA_MAC_VER_80, + RTL_GIGA_MAC_NONE, + RTL_GIGA_MAC_VER_LAST = RTL_GIGA_MAC_NONE - 1 + }; +--- a/drivers/net/ethernet/realtek/r8169_main.c ++++ b/drivers/net/ethernet/realtek/r8169_main.c +@@ -60,6 +60,7 @@ + #define FIRMWARE_8125BP_2 "rtl_nic/rtl8125bp-2.fw" + #define FIRMWARE_8126A_2 "rtl_nic/rtl8126a-2.fw" + #define FIRMWARE_8126A_3 "rtl_nic/rtl8126a-3.fw" ++#define FIRMWARE_8127A_1 "rtl_nic/rtl8127a-1.fw" + + #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ + #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ +@@ -98,6 +99,9 @@ static const struct rtl_chip_info { + const char *name; + const char *fw_name; + } rtl_chip_infos[] = { ++ /* 8127A family. */ ++ { 0x7cf, 0x6c9, RTL_GIGA_MAC_VER_80, "RTL8127A", FIRMWARE_8127A_1 }, ++ + /* 8126A family. */ + { 0x7cf, 0x64a, RTL_GIGA_MAC_VER_70, "RTL8126A", FIRMWARE_8126A_3 }, + { 0x7cf, 0x649, RTL_GIGA_MAC_VER_70, "RTL8126A", FIRMWARE_8126A_2 }, +@@ -222,8 +226,10 @@ static const struct pci_device_id rtl816 + { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, + { PCI_VDEVICE(REALTEK, 0x8125) }, + { PCI_VDEVICE(REALTEK, 0x8126) }, ++ { PCI_VDEVICE(REALTEK, 0x8127) }, + { PCI_VDEVICE(REALTEK, 0x3000) }, + { PCI_VDEVICE(REALTEK, 0x5000) }, ++ { PCI_VDEVICE(REALTEK, 0x0e10) }, + {} + }; + +@@ -770,6 +776,7 @@ MODULE_FIRMWARE(FIRMWARE_8125D_2); + MODULE_FIRMWARE(FIRMWARE_8125BP_2); + MODULE_FIRMWARE(FIRMWARE_8126A_2); + MODULE_FIRMWARE(FIRMWARE_8126A_3); ++MODULE_FIRMWARE(FIRMWARE_8127A_1); + + static inline struct device *tp_to_dev(struct rtl8169_private *tp) + { +@@ -2941,6 +2948,7 @@ static void rtl_hw_aspm_clkreq_enable(st + rtl_mod_config5(tp, 0, ASPM_en); + switch (tp->mac_version) { + case RTL_GIGA_MAC_VER_70: ++ case RTL_GIGA_MAC_VER_80: + val8 = RTL_R8(tp, INT_CFG0_8125) | INT_CFG0_CLKREQEN; + RTL_W8(tp, INT_CFG0_8125, val8); + break; +@@ -2972,6 +2980,7 @@ static void rtl_hw_aspm_clkreq_enable(st + + switch (tp->mac_version) { + case RTL_GIGA_MAC_VER_70: ++ case RTL_GIGA_MAC_VER_80: + val8 = RTL_R8(tp, INT_CFG0_8125) & ~INT_CFG0_CLKREQEN; + RTL_W8(tp, INT_CFG0_8125, val8); + break; +@@ -3691,10 +3700,13 @@ static void rtl_hw_start_8125_common(str + /* disable new tx descriptor format */ + r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); + +- if (tp->mac_version == RTL_GIGA_MAC_VER_70) ++ if (tp->mac_version == RTL_GIGA_MAC_VER_70 || ++ tp->mac_version == RTL_GIGA_MAC_VER_80) + RTL_W8(tp, 0xD8, RTL_R8(tp, 0xD8) & ~0x02); + +- if (tp->mac_version == RTL_GIGA_MAC_VER_70) ++ if (tp->mac_version == RTL_GIGA_MAC_VER_80) ++ r8168_mac_ocp_modify(tp, 0xe614, 0x0f00, 0x0f00); ++ else if (tp->mac_version == RTL_GIGA_MAC_VER_70) + r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); + else if (tp->mac_version == RTL_GIGA_MAC_VER_63) + r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); +@@ -3712,7 +3724,8 @@ static void rtl_hw_start_8125_common(str + r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); + r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); + r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); +- if (tp->mac_version == RTL_GIGA_MAC_VER_70) ++ if (tp->mac_version == RTL_GIGA_MAC_VER_70 || ++ tp->mac_version == RTL_GIGA_MAC_VER_80) + r8168_mac_ocp_modify(tp, 0xea1c, 0x0300, 0x0000); + else + r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); +@@ -3790,6 +3803,12 @@ static void rtl_hw_start_8126a(struct rt + rtl_hw_start_8125_common(tp); + } + ++static void rtl_hw_start_8127a(struct rtl8169_private *tp) ++{ ++ rtl_set_def_aspm_entry_latency(tp); ++ rtl_hw_start_8125_common(tp); ++} ++ + static void rtl_hw_config(struct rtl8169_private *tp) + { + static const rtl_generic_fct hw_configs[] = { +@@ -3833,6 +3852,7 @@ static void rtl_hw_config(struct rtl8169 + [RTL_GIGA_MAC_VER_64] = rtl_hw_start_8125d, + [RTL_GIGA_MAC_VER_66] = rtl_hw_start_8125d, + [RTL_GIGA_MAC_VER_70] = rtl_hw_start_8126a, ++ [RTL_GIGA_MAC_VER_80] = rtl_hw_start_8127a, + }; + + if (hw_configs[tp->mac_version]) +@@ -3850,8 +3870,11 @@ static void rtl_hw_start_8125(struct rtl + case RTL_GIGA_MAC_VER_61: + case RTL_GIGA_MAC_VER_64: + case RTL_GIGA_MAC_VER_66: ++ case RTL_GIGA_MAC_VER_80: + for (i = 0xa00; i < 0xb00; i += 4) + RTL_W32(tp, i, 0); ++ if (tp->mac_version == RTL_GIGA_MAC_VER_80) ++ RTL_W16(tp, INT_CFG1_8125, 0x0000); + break; + case RTL_GIGA_MAC_VER_63: + case RTL_GIGA_MAC_VER_70: +--- a/drivers/net/ethernet/realtek/r8169_phy_config.c ++++ b/drivers/net/ethernet/realtek/r8169_phy_config.c +@@ -1130,6 +1130,171 @@ static void rtl8126a_hw_phy_config(struc + rtl8125_common_config_eee_phy(phydev); + } + ++static void rtl8127a_1_hw_phy_config(struct rtl8169_private *tp, ++ struct phy_device *phydev) ++{ ++ r8169_apply_firmware(tp); ++ rtl8168g_enable_gphy_10m(phydev); ++ ++ r8168g_phy_param(phydev, 0x8415, 0xff00, 0x9300); ++ r8168g_phy_param(phydev, 0x81a3, 0xff00, 0x0f00); ++ r8168g_phy_param(phydev, 0x81ae, 0xff00, 0x0f00); ++ r8168g_phy_param(phydev, 0x81b9, 0xff00, 0xb900); ++ rtl8125_phy_param(phydev, 0x83b0, 0x0e00, 0x0000); ++ rtl8125_phy_param(phydev, 0x83C5, 0x0e00, 0x0000); ++ rtl8125_phy_param(phydev, 0x83da, 0x0e00, 0x0000); ++ rtl8125_phy_param(phydev, 0x83ef, 0x0e00, 0x0000); ++ phy_modify_paged(phydev, 0x0bf3, 0x14, 0x01f0, 0x0160); ++ phy_modify_paged(phydev, 0x0bf3, 0x15, 0x001f, 0x0014); ++ phy_modify_paged(phydev, 0x0bf2, 0x14, 0x6000, 0x0000); ++ phy_modify_paged(phydev, 0x0bf2, 0x16, 0xc000, 0x0000); ++ phy_modify_paged(phydev, 0x0bf2, 0x14, 0x1fff, 0x0187); ++ phy_modify_paged(phydev, 0x0bf2, 0x15, 0x003f, 0x0003); ++ ++ r8168g_phy_param(phydev, 0x8173, 0xffff, 0x8620); ++ r8168g_phy_param(phydev, 0x8175, 0xffff, 0x8671); ++ r8168g_phy_param(phydev, 0x817c, 0x0000, 0x2000); ++ r8168g_phy_param(phydev, 0x8187, 0x0000, 0x2000); ++ r8168g_phy_param(phydev, 0x8192, 0x0000, 0x2000); ++ r8168g_phy_param(phydev, 0x819d, 0x0000, 0x2000); ++ r8168g_phy_param(phydev, 0x81a8, 0x2000, 0x0000); ++ r8168g_phy_param(phydev, 0x81b3, 0x2000, 0x0000); ++ r8168g_phy_param(phydev, 0x81be, 0x0000, 0x2000); ++ r8168g_phy_param(phydev, 0x817d, 0xff00, 0xa600); ++ r8168g_phy_param(phydev, 0x8188, 0xff00, 0xa600); ++ r8168g_phy_param(phydev, 0x8193, 0xff00, 0xa600); ++ r8168g_phy_param(phydev, 0x819e, 0xff00, 0xa600); ++ r8168g_phy_param(phydev, 0x81a9, 0xff00, 0x1400); ++ r8168g_phy_param(phydev, 0x81b4, 0xff00, 0x1400); ++ r8168g_phy_param(phydev, 0x81bf, 0xff00, 0xa600); ++ ++ phy_modify_paged(phydev, 0x0aea, 0x15, 0x0028, 0x0000); ++ ++ rtl8125_phy_param(phydev, 0x84f0, 0xffff, 0x201c); ++ rtl8125_phy_param(phydev, 0x84f2, 0xffff, 0x3117); ++ ++ phy_write_paged(phydev, 0x0aec, 0x13, 0x0000); ++ phy_write_paged(phydev, 0x0ae2, 0x10, 0xffff); ++ phy_write_paged(phydev, 0x0aec, 0x17, 0xffff); ++ phy_write_paged(phydev, 0x0aed, 0x11, 0xffff); ++ phy_write_paged(phydev, 0x0aec, 0x14, 0x0000); ++ phy_modify_paged(phydev, 0x0aed, 0x10, 0x0001, 0x0000); ++ phy_write_paged(phydev, 0x0adb, 0x14, 0x0150); ++ rtl8125_phy_param(phydev, 0x8197, 0xff00, 0x5000); ++ rtl8125_phy_param(phydev, 0x8231, 0xff00, 0x5000); ++ rtl8125_phy_param(phydev, 0x82cb, 0xff00, 0x5000); ++ rtl8125_phy_param(phydev, 0x82cd, 0xff00, 0x5700); ++ rtl8125_phy_param(phydev, 0x8233, 0xff00, 0x5700); ++ rtl8125_phy_param(phydev, 0x8199, 0xff00, 0x5700); ++ ++ rtl8125_phy_param(phydev, 0x815a, 0xffff, 0x0150); ++ rtl8125_phy_param(phydev, 0x81f4, 0xffff, 0x0150); ++ rtl8125_phy_param(phydev, 0x828e, 0xffff, 0x0150); ++ rtl8125_phy_param(phydev, 0x81b1, 0xffff, 0x0000); ++ rtl8125_phy_param(phydev, 0x824b, 0xffff, 0x0000); ++ rtl8125_phy_param(phydev, 0x82e5, 0xffff, 0x0000); ++ ++ rtl8125_phy_param(phydev, 0x84f7, 0xff00, 0x2800); ++ phy_modify_paged(phydev, 0x0aec, 0x11, 0x0000, 0x1000); ++ rtl8125_phy_param(phydev, 0x81b3, 0xff00, 0xad00); ++ rtl8125_phy_param(phydev, 0x824d, 0xff00, 0xad00); ++ rtl8125_phy_param(phydev, 0x82e7, 0xff00, 0xad00); ++ phy_modify_paged(phydev, 0x0ae4, 0x17, 0x000f, 0x0001); ++ rtl8125_phy_param(phydev, 0x82ce, 0xf000, 0x4000); ++ ++ rtl8125_phy_param(phydev, 0x84ac, 0xffff, 0x0000); ++ rtl8125_phy_param(phydev, 0x84ae, 0xffff, 0x0000); ++ rtl8125_phy_param(phydev, 0x84b0, 0xffff, 0xf818); ++ rtl8125_phy_param(phydev, 0x84b2, 0xff00, 0x6000); ++ ++ rtl8125_phy_param(phydev, 0x8ffc, 0xffff, 0x6008); ++ rtl8125_phy_param(phydev, 0x8ffe, 0xffff, 0xf450); ++ ++ rtl8125_phy_param(phydev, 0x8015, 0x0000, 0x0200); ++ rtl8125_phy_param(phydev, 0x8016, 0x0800, 0x0000); ++ rtl8125_phy_param(phydev, 0x8fe6, 0xff00, 0x0800); ++ rtl8125_phy_param(phydev, 0x8fe4, 0xffff, 0x2114); ++ ++ rtl8125_phy_param(phydev, 0x8647, 0xffff, 0xa7b1); ++ rtl8125_phy_param(phydev, 0x8649, 0xffff, 0xbbca); ++ rtl8125_phy_param(phydev, 0x864b, 0xff00, 0xdc00); ++ ++ rtl8125_phy_param(phydev, 0x8154, 0xc000, 0x4000); ++ rtl8125_phy_param(phydev, 0x8158, 0xc000, 0x0000); ++ ++ rtl8125_phy_param(phydev, 0x826c, 0xffff, 0xffff); ++ rtl8125_phy_param(phydev, 0x826e, 0xffff, 0xffff); ++ ++ rtl8125_phy_param(phydev, 0x8872, 0xff00, 0x0e00); ++ r8168g_phy_param(phydev, 0x8012, 0x0000, 0x0800); ++ r8168g_phy_param(phydev, 0x8012, 0x0000, 0x4000); ++ phy_modify_paged(phydev, 0x0b57, 0x13, 0x0000, 0x0001); ++ r8168g_phy_param(phydev, 0x834a, 0xff00, 0x0700); ++ rtl8125_phy_param(phydev, 0x8217, 0x3f00, 0x2a00); ++ r8168g_phy_param(phydev, 0x81b1, 0xff00, 0x0b00); ++ rtl8125_phy_param(phydev, 0x8fed, 0xff00, 0x4e00); ++ ++ rtl8125_phy_param(phydev, 0x88ac, 0xff00, 0x2300); ++ phy_modify_paged(phydev, 0x0bf0, 0x16, 0x0000, 0x3800); ++ rtl8125_phy_param(phydev, 0x88de, 0xff00, 0x0000); ++ rtl8125_phy_param(phydev, 0x80b4, 0xffff, 0x5195); ++ ++ r8168g_phy_param(phydev, 0x8370, 0xffff, 0x8671); ++ r8168g_phy_param(phydev, 0x8372, 0xffff, 0x86c8); ++ ++ r8168g_phy_param(phydev, 0x8401, 0xffff, 0x86c8); ++ r8168g_phy_param(phydev, 0x8403, 0xffff, 0x86da); ++ r8168g_phy_param(phydev, 0x8406, 0x1800, 0x1000); ++ r8168g_phy_param(phydev, 0x8408, 0x1800, 0x1000); ++ r8168g_phy_param(phydev, 0x840a, 0x1800, 0x1000); ++ r8168g_phy_param(phydev, 0x840c, 0x1800, 0x1000); ++ r8168g_phy_param(phydev, 0x840e, 0x1800, 0x1000); ++ r8168g_phy_param(phydev, 0x8410, 0x1800, 0x1000); ++ r8168g_phy_param(phydev, 0x8412, 0x1800, 0x1000); ++ r8168g_phy_param(phydev, 0x8414, 0x1800, 0x1000); ++ r8168g_phy_param(phydev, 0x8416, 0x1800, 0x1000); ++ ++ r8168g_phy_param(phydev, 0x82bd, 0xffff, 0x1f40); ++ ++ phy_modify_paged(phydev, 0x0bfb, 0x12, 0x07ff, 0x0328); ++ phy_write_paged(phydev, 0x0bfb, 0x13, 0x3e14); ++ ++ r8168g_phy_param(phydev, 0x81c4, 0xffff, 0x003b); ++ r8168g_phy_param(phydev, 0x81c6, 0xffff, 0x0086); ++ r8168g_phy_param(phydev, 0x81c8, 0xffff, 0x00b7); ++ r8168g_phy_param(phydev, 0x81ca, 0xffff, 0x00db); ++ r8168g_phy_param(phydev, 0x81cc, 0xffff, 0x00fe); ++ r8168g_phy_param(phydev, 0x81ce, 0xffff, 0x00fe); ++ r8168g_phy_param(phydev, 0x81d0, 0xffff, 0x00fe); ++ r8168g_phy_param(phydev, 0x81d2, 0xffff, 0x00fe); ++ r8168g_phy_param(phydev, 0x81d4, 0xffff, 0x00c3); ++ r8168g_phy_param(phydev, 0x81d6, 0xffff, 0x0078); ++ r8168g_phy_param(phydev, 0x81d8, 0xffff, 0x0047); ++ r8168g_phy_param(phydev, 0x81da, 0xffff, 0x0023); ++ ++ rtl8125_phy_param(phydev, 0x88d7, 0xffff, 0x01a0); ++ rtl8125_phy_param(phydev, 0x88d9, 0xffff, 0x01a0); ++ rtl8125_phy_param(phydev, 0x8ffa, 0xffff, 0x002a); ++ ++ rtl8125_phy_param(phydev, 0x8fee, 0xffff, 0xffdf); ++ rtl8125_phy_param(phydev, 0x8ff0, 0xffff, 0xffff); ++ rtl8125_phy_param(phydev, 0x8ff2, 0xffff, 0x0a4a); ++ rtl8125_phy_param(phydev, 0x8ff4, 0xffff, 0xaa5a); ++ rtl8125_phy_param(phydev, 0x8ff6, 0xffff, 0x0a4a); ++ ++ rtl8125_phy_param(phydev, 0x8ff8, 0xffff, 0xaa5a); ++ rtl8125_phy_param(phydev, 0x88d5, 0xff00, 0x0200); ++ ++ r8168g_phy_param(phydev, 0x84bb, 0xff00, 0x0a00); ++ r8168g_phy_param(phydev, 0x84c0, 0xff00, 0x1600); ++ ++ phy_modify_paged(phydev, 0x0a43, 0x10, 0x0000, 0x0003); ++ ++ rtl8125_legacy_force_mode(phydev); ++ rtl8168g_disable_aldps(phydev); ++ rtl8125_common_config_eee_phy(phydev); ++} ++ + void r8169_hw_phy_config(struct rtl8169_private *tp, struct phy_device *phydev, + enum mac_version ver) + { +@@ -1181,6 +1346,7 @@ void r8169_hw_phy_config(struct rtl8169_ + [RTL_GIGA_MAC_VER_64] = rtl8125d_hw_phy_config, + [RTL_GIGA_MAC_VER_66] = rtl8125bp_hw_phy_config, + [RTL_GIGA_MAC_VER_70] = rtl8126a_hw_phy_config, ++ [RTL_GIGA_MAC_VER_80] = rtl8127a_1_hw_phy_config, + }; + + if (phy_configs[ver])