From: Julian Seward Date: Fri, 3 Sep 2010 23:49:33 +0000 (+0000) Subject: Add tests for new PowerISA_2.05 instructions available on Power6 CPUs. X-Git-Tag: svn/VALGRIND_3_6_0~119 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=9287d802b4004e8c728c8c53b4c74710ecd74ffe;p=thirdparty%2Fvalgrind.git Add tests for new PowerISA_2.05 instructions available on Power6 CPUs. (Maynard Johnson, maynardj@us.ibm.com and Pete Eberlein, eberlein@us.ibm.com) git-svn-id: svn://svn.valgrind.org/valgrind/trunk@11338 --- diff --git a/configure.in b/configure.in index aaf459fb61..a47fede39f 100644 --- a/configure.in +++ b/configure.in @@ -935,6 +935,7 @@ AC_MSG_RESULT([no]) ]) CFLAGS=$safe_CFLAGS +AM_CONDITIONAL([HAS_ALTIVEC], [test x$ac_have_altivec = xyes]) # Check for pthread_create@GLIBC2.0 @@ -1875,6 +1876,8 @@ AC_CONFIG_FILES([ memcheck/tests/darwin/Makefile memcheck/tests/amd64-linux/Makefile memcheck/tests/x86-linux/Makefile + memcheck/tests/ppc32/Makefile + memcheck/tests/ppc64/Makefile memcheck/perf/Makefile cachegrind/Makefile cachegrind/tests/Makefile diff --git a/memcheck/tests/Makefile.am b/memcheck/tests/Makefile.am index 3ad021092c..550b6d635a 100644 --- a/memcheck/tests/Makefile.am +++ b/memcheck/tests/Makefile.am @@ -11,6 +11,13 @@ if VGCONF_ARCHS_INCLUDE_AMD64 SUBDIRS += amd64 endif +if VGCONF_ARCHS_INCLUDE_PPC32 +SUBDIRS += ppc32 +endif +if VGCONF_ARCHS_INCLUDE_PPC64 +SUBDIRS += ppc64 +endif + # OS-specific tests if VGCONF_OS_IS_LINUX SUBDIRS += linux diff --git a/memcheck/tests/ppc32/Makefile.am b/memcheck/tests/ppc32/Makefile.am new file mode 100644 index 0000000000..86bd3a5ed6 --- /dev/null +++ b/memcheck/tests/ppc32/Makefile.am @@ -0,0 +1,11 @@ + +noinst_SCRIPTS = filter_stderr + +EXTRA_DIST = $(noinst_SCRIPTS) \ + power_ISA2_05.stderr.exp power_ISA2_05.stdout.exp power_ISA2_05.vgtest + +check_PROGRAMS = \ + power_ISA2_05 + +AM_CFLAGS = $(WERROR) -Winline -Wall -Wshadow -g -I$(top_srcdir)/include @FLAG_M32@ +AM_CXXFLAGS = $(AM_CFLAGS) @FLAG_M32@ diff --git a/memcheck/tests/ppc32/filter_stderr b/memcheck/tests/ppc32/filter_stderr new file mode 100755 index 0000000000..0ae9313a9f --- /dev/null +++ b/memcheck/tests/ppc32/filter_stderr @@ -0,0 +1,3 @@ +#! /bin/sh + +../filter_stderr diff --git a/memcheck/tests/ppc32/power_ISA2_05.c b/memcheck/tests/ppc32/power_ISA2_05.c new file mode 100644 index 0000000000..82893a2976 --- /dev/null +++ b/memcheck/tests/ppc32/power_ISA2_05.c @@ -0,0 +1,207 @@ +#include + +double foo = -1.0; +double FRT1; +double FRT2; +int base256(int val) +{ +/* interpret the bitstream representing val as a base 256 number for testing + * the parity instrs + */ + int sum = 0; + int scale = 1; + int i; + + for (i = 0; i < 8; i++) { + int bit = val & 1; + sum = sum + bit * scale; + val <<= 1; + scale *= 256; + } + return sum; +} + +void test_parity_instrs() +{ + unsigned long long_word; + unsigned int word; + int i, parity; + + for (i = 0; i < 50; i++) { + word = base256(i); + long_word = word; + __asm__ volatile ("prtyd %0, %1":"=r" (parity):"r"(long_word)); + printf("prtyd (%x) => parity=%x\n", i, parity); + __asm__ volatile ("prtyw %0, %1":"=r" (parity):"r"(word)); + printf("prtyw (%x) => parity=%x\n", i, parity); + } +} + +void test_lfiwax() +{ + unsigned long base; + unsigned long offset; + + typedef struct { + unsigned int hi; + unsigned int lo; + } int_pair_t; + + int_pair_t *ip; + foo = -1024.0; + base = (unsigned long) &foo; + offset = 0; + __asm__ volatile ("lfiwax %0, %1, %2":"=f" (FRT1):"r"(base), + "r"(offset)); + ip = (int_pair_t *) & FRT1; + printf("lfiwax (%f) => FRT=(%x, %x)\n", foo, ip->hi, ip->lo); + + +} + + + +/* lfdp FPp, DS(RA) : load float double pair +** FPp = leftmost 64 bits stored at DS(RA) +** FPp+1= rightmost 64 bits stored at DS(RA) +** FPp must be an even float register +*/ +int test_double_pair_instrs() +{ + typedef struct { + double hi; + double lo; + } dbl_pair_t; + + /* the following decls are for alignment */ + int i; + int j; + int k; + int l; +#ifdef __powerpc64__ + int m; + int n; + int o; +#endif + dbl_pair_t dbl_pair[3]; /* must be quad word aligned */ + unsigned long base; + unsigned long offset; + + for (i = 0; i < 3; i++) { + dbl_pair[i].hi = -1024.0 + i; + dbl_pair[i].lo = 1024.0 + i + 1; + } + + __asm__ volatile ("lfdp 10, %0"::"m" (dbl_pair[0])); + __asm__ volatile ("fmr %0, 10":"=f" (FRT1)); + __asm__ volatile ("fmr %0, 11":"=f" (FRT2)); + printf("lfdp (%f, %f) => F_hi=%f, F_lo=%f\n", + dbl_pair[0].hi, dbl_pair[0].lo, FRT1, FRT2); + + + FRT1 = 2.2048; + FRT2 = -4.1024; + __asm__ volatile ("fmr 10, %0"::"f" (FRT1)); + __asm__ volatile ("fmr 11, %0"::"f" (FRT2)); + __asm__ volatile ("stfdp 10, %0"::"m" (dbl_pair[1])); + printf("stfdp (%f, %f) => F_hi=%f, F_lo=%f\n", + FRT1, FRT2, dbl_pair[1].hi, dbl_pair[1].lo); + + FRT1 = 0.0; + FRT2 = -1.0; + base = (unsigned long) &dbl_pair; + offset = (unsigned long) &dbl_pair[1] - base; + __asm__ volatile ("or 20, 0, %0"::"r" (base)); + __asm__ volatile ("or 21, 0, %0"::"r" (offset)); + __asm__ volatile ("lfdpx 10, 20, 21"); + __asm__ volatile ("fmr %0, 10":"=f" (FRT1)); + __asm__ volatile ("fmr %0, 11":"=f" (FRT2)); + printf("lfdpx (%f, %f) => F_hi=%f, F_lo=%f\n", + dbl_pair[1].hi, dbl_pair[1].lo, FRT1, FRT2); + + FRT1 = 8.2048; + FRT2 = -16.1024; + base = (unsigned long) &dbl_pair; + offset = (unsigned long) &dbl_pair[2] - base; + __asm__ volatile ("or 20, 0, %0"::"r" (base)); + __asm__ volatile ("or 21, 0, %0"::"r" (offset)); + __asm__ volatile ("fmr %0, 10":"=f" (FRT1)); + __asm__ volatile ("fmr %0, 11":"=f" (FRT2)); + __asm__ volatile ("stfdpx 10, 20, 21"); + printf("stfdpx (%f, %f) => F_hi=%f, F_lo=%f\n", + FRT1, FRT2, dbl_pair[2].hi, dbl_pair[2].lo); +#ifdef __powerpc64__ + return i + j + k + l + m + n + o; +#else + return i + j + k + l; +#endif +} + + +/* The contents of FRB with bit set 0 set to bit 0 of FRA copied into FRT */ +void test_fcpsgn() +{ + double A[] = { + 10.101010, + -0.0, + 0.0, + -10.101010 + }; + + double B[] = { + 11.111111, + -0.0, + 0.0, + -11.111111 + }; + + double FRT, FRA, FRB; + int i, j; + + for (i = 0; i < 4; i++) { + FRA = A[i]; + for (j = 0; j < 4; j++) { + FRB = B[j]; + __asm__ volatile ("fcpsgn %0, %1, %2":"=f" (FRT):"f"(FRA), + "f"(FRB)); + printf("fcpsgn sign=%f, base=%f => %f\n", FRA, FRB, FRT); + } + } +} + +/* b0 may be non-zero in lwarx/ldarx Power6 instrs */ +int test_reservation() +{ + + int RT; + int i, j; + unsigned long base; + unsigned long offset; + long arr[4] = { 0xdeadbeef, 0xbad0beef, 0xbeefdead, 0xbeef0bad }; + + + base = (unsigned long) &arr; + offset = (unsigned long) &arr[1] - base; + __asm__ volatile ("or 20, 0, %0"::"r" (base)); + __asm__ volatile ("or 21, 0, %0"::"r" (offset)); + __asm__ volatile ("lwarx %0, 20, 21, 1":"=r" (RT)); + printf("lwarx => %x\n", RT); + +#ifdef __powerpc64__ + offset = (unsigned long) &arr[1] - base; + __asm__ volatile ("or 21, 0, %0"::"r" (offset)); + __asm__ volatile ("ldarx %0, 20, 21, 1":"=r" (RT)); + printf("ldarx => %x\n", RT); +#endif + return i + j; +} + +int main(void) +{ + (void) test_reservation(); + test_fcpsgn(); + (void) test_double_pair_instrs(); + test_lfiwax(); + test_parity_instrs(); + return 0; +} diff --git a/memcheck/tests/ppc32/power_ISA2_05.stderr.exp b/memcheck/tests/ppc32/power_ISA2_05.stderr.exp new file mode 100644 index 0000000000..c22dd7f4c0 --- /dev/null +++ b/memcheck/tests/ppc32/power_ISA2_05.stderr.exp @@ -0,0 +1,10 @@ + + +HEAP SUMMARY: + in use at exit: 0 bytes in 0 blocks + total heap usage: 0 allocs, 0 frees, 0 bytes allocated + +For a detailed leak analysis, rerun with: --leak-check=full + +For counts of detected and suppressed errors, rerun with: -v +ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from 0) diff --git a/memcheck/tests/ppc32/power_ISA2_05.stdout.exp b/memcheck/tests/ppc32/power_ISA2_05.stdout.exp new file mode 100644 index 0000000000..5513960418 --- /dev/null +++ b/memcheck/tests/ppc32/power_ISA2_05.stdout.exp @@ -0,0 +1,122 @@ +lwarx => bad0beef +fcpsgn sign=10.101010, base=11.111111 => 11.111111 +fcpsgn sign=10.101010, base=-0.000000 => 0.000000 +fcpsgn sign=10.101010, base=0.000000 => 0.000000 +fcpsgn sign=10.101010, base=-11.111111 => 11.111111 +fcpsgn sign=-0.000000, base=11.111111 => -11.111111 +fcpsgn sign=-0.000000, base=-0.000000 => -0.000000 +fcpsgn sign=-0.000000, base=0.000000 => -0.000000 +fcpsgn sign=-0.000000, base=-11.111111 => -11.111111 +fcpsgn sign=0.000000, base=11.111111 => 11.111111 +fcpsgn sign=0.000000, base=-0.000000 => 0.000000 +fcpsgn sign=0.000000, base=0.000000 => 0.000000 +fcpsgn sign=0.000000, base=-11.111111 => 11.111111 +fcpsgn sign=-10.101010, base=11.111111 => -11.111111 +fcpsgn sign=-10.101010, base=-0.000000 => -0.000000 +fcpsgn sign=-10.101010, base=0.000000 => -0.000000 +fcpsgn sign=-10.101010, base=-11.111111 => -11.111111 +lfdp (-1024.000000, 1025.000000) => F_hi=-1024.000000, F_lo=1025.000000 +stfdp (2.204800, -4.102400) => F_hi=2.204800, F_lo=-4.102400 +lfdpx (2.204800, -4.102400) => F_hi=2.204800, F_lo=-4.102400 +stfdpx (2.204800, 2.204800) => F_hi=2.204800, F_lo=2.204800 +lfiwax (-1024.000000) => FRT=(ffffffff, c0900000) +prtyd (0) => parity=0 +prtyw (0) => parity=0 +prtyd (1) => parity=1 +prtyw (1) => parity=1 +prtyd (2) => parity=0 +prtyw (2) => parity=0 +prtyd (3) => parity=1 +prtyw (3) => parity=1 +prtyd (4) => parity=0 +prtyw (4) => parity=0 +prtyd (5) => parity=1 +prtyw (5) => parity=1 +prtyd (6) => parity=0 +prtyw (6) => parity=0 +prtyd (7) => parity=1 +prtyw (7) => parity=1 +prtyd (8) => parity=0 +prtyw (8) => parity=0 +prtyd (9) => parity=1 +prtyw (9) => parity=1 +prtyd (a) => parity=0 +prtyw (a) => parity=0 +prtyd (b) => parity=1 +prtyw (b) => parity=1 +prtyd (c) => parity=0 +prtyw (c) => parity=0 +prtyd (d) => parity=1 +prtyw (d) => parity=1 +prtyd (e) => parity=0 +prtyw (e) => parity=0 +prtyd (f) => parity=1 +prtyw (f) => parity=1 +prtyd (10) => parity=0 +prtyw (10) => parity=0 +prtyd (11) => parity=1 +prtyw (11) => parity=1 +prtyd (12) => parity=0 +prtyw (12) => parity=0 +prtyd (13) => parity=1 +prtyw (13) => parity=1 +prtyd (14) => parity=0 +prtyw (14) => parity=0 +prtyd (15) => parity=1 +prtyw (15) => parity=1 +prtyd (16) => parity=0 +prtyw (16) => parity=0 +prtyd (17) => parity=1 +prtyw (17) => parity=1 +prtyd (18) => parity=0 +prtyw (18) => parity=0 +prtyd (19) => parity=1 +prtyw (19) => parity=1 +prtyd (1a) => parity=0 +prtyw (1a) => parity=0 +prtyd (1b) => parity=1 +prtyw (1b) => parity=1 +prtyd (1c) => parity=0 +prtyw (1c) => parity=0 +prtyd (1d) => parity=1 +prtyw (1d) => parity=1 +prtyd (1e) => parity=0 +prtyw (1e) => parity=0 +prtyd (1f) => parity=1 +prtyw (1f) => parity=1 +prtyd (20) => parity=0 +prtyw (20) => parity=0 +prtyd (21) => parity=1 +prtyw (21) => parity=1 +prtyd (22) => parity=0 +prtyw (22) => parity=0 +prtyd (23) => parity=1 +prtyw (23) => parity=1 +prtyd (24) => parity=0 +prtyw (24) => parity=0 +prtyd (25) => parity=1 +prtyw (25) => parity=1 +prtyd (26) => parity=0 +prtyw (26) => parity=0 +prtyd (27) => parity=1 +prtyw (27) => parity=1 +prtyd (28) => parity=0 +prtyw (28) => parity=0 +prtyd (29) => parity=1 +prtyw (29) => parity=1 +prtyd (2a) => parity=0 +prtyw (2a) => parity=0 +prtyd (2b) => parity=1 +prtyw (2b) => parity=1 +prtyd (2c) => parity=0 +prtyw (2c) => parity=0 +prtyd (2d) => parity=1 +prtyw (2d) => parity=1 +prtyd (2e) => parity=0 +prtyw (2e) => parity=0 +prtyd (2f) => parity=1 +prtyw (2f) => parity=1 +prtyd (30) => parity=0 +prtyw (30) => parity=0 +prtyd (31) => parity=1 +prtyw (31) => parity=1 diff --git a/memcheck/tests/ppc32/power_ISA2_05.vgtest b/memcheck/tests/ppc32/power_ISA2_05.vgtest new file mode 100644 index 0000000000..712ec3b104 --- /dev/null +++ b/memcheck/tests/ppc32/power_ISA2_05.vgtest @@ -0,0 +1 @@ +prog: power_ISA2_05 diff --git a/memcheck/tests/ppc64/Makefile.am b/memcheck/tests/ppc64/Makefile.am new file mode 100644 index 0000000000..dbb726ae4f --- /dev/null +++ b/memcheck/tests/ppc64/Makefile.am @@ -0,0 +1,12 @@ + +noinst_SCRIPTS = filter_stderr + +EXTRA_DIST = $(noinst_SCRIPTS) \ + power_ISA2_05.stderr.exp power_ISA2_05.stdout.exp power_ISA2_05.vgtest + +check_PROGRAMS = \ + power_ISA2_05 + +AM_CFLAGS = $(WERROR) -Winline -Wall -Wshadow -g -I$(top_srcdir)/include \ + @FLAG_M64@ +AM_CXXFLAGS = $(AM_CFLAGS) @FLAG_M64@ diff --git a/memcheck/tests/ppc64/filter_stderr b/memcheck/tests/ppc64/filter_stderr new file mode 100755 index 0000000000..0ae9313a9f --- /dev/null +++ b/memcheck/tests/ppc64/filter_stderr @@ -0,0 +1,3 @@ +#! /bin/sh + +../filter_stderr diff --git a/memcheck/tests/ppc64/power_ISA2_05.c b/memcheck/tests/ppc64/power_ISA2_05.c new file mode 100644 index 0000000000..82893a2976 --- /dev/null +++ b/memcheck/tests/ppc64/power_ISA2_05.c @@ -0,0 +1,207 @@ +#include + +double foo = -1.0; +double FRT1; +double FRT2; +int base256(int val) +{ +/* interpret the bitstream representing val as a base 256 number for testing + * the parity instrs + */ + int sum = 0; + int scale = 1; + int i; + + for (i = 0; i < 8; i++) { + int bit = val & 1; + sum = sum + bit * scale; + val <<= 1; + scale *= 256; + } + return sum; +} + +void test_parity_instrs() +{ + unsigned long long_word; + unsigned int word; + int i, parity; + + for (i = 0; i < 50; i++) { + word = base256(i); + long_word = word; + __asm__ volatile ("prtyd %0, %1":"=r" (parity):"r"(long_word)); + printf("prtyd (%x) => parity=%x\n", i, parity); + __asm__ volatile ("prtyw %0, %1":"=r" (parity):"r"(word)); + printf("prtyw (%x) => parity=%x\n", i, parity); + } +} + +void test_lfiwax() +{ + unsigned long base; + unsigned long offset; + + typedef struct { + unsigned int hi; + unsigned int lo; + } int_pair_t; + + int_pair_t *ip; + foo = -1024.0; + base = (unsigned long) &foo; + offset = 0; + __asm__ volatile ("lfiwax %0, %1, %2":"=f" (FRT1):"r"(base), + "r"(offset)); + ip = (int_pair_t *) & FRT1; + printf("lfiwax (%f) => FRT=(%x, %x)\n", foo, ip->hi, ip->lo); + + +} + + + +/* lfdp FPp, DS(RA) : load float double pair +** FPp = leftmost 64 bits stored at DS(RA) +** FPp+1= rightmost 64 bits stored at DS(RA) +** FPp must be an even float register +*/ +int test_double_pair_instrs() +{ + typedef struct { + double hi; + double lo; + } dbl_pair_t; + + /* the following decls are for alignment */ + int i; + int j; + int k; + int l; +#ifdef __powerpc64__ + int m; + int n; + int o; +#endif + dbl_pair_t dbl_pair[3]; /* must be quad word aligned */ + unsigned long base; + unsigned long offset; + + for (i = 0; i < 3; i++) { + dbl_pair[i].hi = -1024.0 + i; + dbl_pair[i].lo = 1024.0 + i + 1; + } + + __asm__ volatile ("lfdp 10, %0"::"m" (dbl_pair[0])); + __asm__ volatile ("fmr %0, 10":"=f" (FRT1)); + __asm__ volatile ("fmr %0, 11":"=f" (FRT2)); + printf("lfdp (%f, %f) => F_hi=%f, F_lo=%f\n", + dbl_pair[0].hi, dbl_pair[0].lo, FRT1, FRT2); + + + FRT1 = 2.2048; + FRT2 = -4.1024; + __asm__ volatile ("fmr 10, %0"::"f" (FRT1)); + __asm__ volatile ("fmr 11, %0"::"f" (FRT2)); + __asm__ volatile ("stfdp 10, %0"::"m" (dbl_pair[1])); + printf("stfdp (%f, %f) => F_hi=%f, F_lo=%f\n", + FRT1, FRT2, dbl_pair[1].hi, dbl_pair[1].lo); + + FRT1 = 0.0; + FRT2 = -1.0; + base = (unsigned long) &dbl_pair; + offset = (unsigned long) &dbl_pair[1] - base; + __asm__ volatile ("or 20, 0, %0"::"r" (base)); + __asm__ volatile ("or 21, 0, %0"::"r" (offset)); + __asm__ volatile ("lfdpx 10, 20, 21"); + __asm__ volatile ("fmr %0, 10":"=f" (FRT1)); + __asm__ volatile ("fmr %0, 11":"=f" (FRT2)); + printf("lfdpx (%f, %f) => F_hi=%f, F_lo=%f\n", + dbl_pair[1].hi, dbl_pair[1].lo, FRT1, FRT2); + + FRT1 = 8.2048; + FRT2 = -16.1024; + base = (unsigned long) &dbl_pair; + offset = (unsigned long) &dbl_pair[2] - base; + __asm__ volatile ("or 20, 0, %0"::"r" (base)); + __asm__ volatile ("or 21, 0, %0"::"r" (offset)); + __asm__ volatile ("fmr %0, 10":"=f" (FRT1)); + __asm__ volatile ("fmr %0, 11":"=f" (FRT2)); + __asm__ volatile ("stfdpx 10, 20, 21"); + printf("stfdpx (%f, %f) => F_hi=%f, F_lo=%f\n", + FRT1, FRT2, dbl_pair[2].hi, dbl_pair[2].lo); +#ifdef __powerpc64__ + return i + j + k + l + m + n + o; +#else + return i + j + k + l; +#endif +} + + +/* The contents of FRB with bit set 0 set to bit 0 of FRA copied into FRT */ +void test_fcpsgn() +{ + double A[] = { + 10.101010, + -0.0, + 0.0, + -10.101010 + }; + + double B[] = { + 11.111111, + -0.0, + 0.0, + -11.111111 + }; + + double FRT, FRA, FRB; + int i, j; + + for (i = 0; i < 4; i++) { + FRA = A[i]; + for (j = 0; j < 4; j++) { + FRB = B[j]; + __asm__ volatile ("fcpsgn %0, %1, %2":"=f" (FRT):"f"(FRA), + "f"(FRB)); + printf("fcpsgn sign=%f, base=%f => %f\n", FRA, FRB, FRT); + } + } +} + +/* b0 may be non-zero in lwarx/ldarx Power6 instrs */ +int test_reservation() +{ + + int RT; + int i, j; + unsigned long base; + unsigned long offset; + long arr[4] = { 0xdeadbeef, 0xbad0beef, 0xbeefdead, 0xbeef0bad }; + + + base = (unsigned long) &arr; + offset = (unsigned long) &arr[1] - base; + __asm__ volatile ("or 20, 0, %0"::"r" (base)); + __asm__ volatile ("or 21, 0, %0"::"r" (offset)); + __asm__ volatile ("lwarx %0, 20, 21, 1":"=r" (RT)); + printf("lwarx => %x\n", RT); + +#ifdef __powerpc64__ + offset = (unsigned long) &arr[1] - base; + __asm__ volatile ("or 21, 0, %0"::"r" (offset)); + __asm__ volatile ("ldarx %0, 20, 21, 1":"=r" (RT)); + printf("ldarx => %x\n", RT); +#endif + return i + j; +} + +int main(void) +{ + (void) test_reservation(); + test_fcpsgn(); + (void) test_double_pair_instrs(); + test_lfiwax(); + test_parity_instrs(); + return 0; +} diff --git a/memcheck/tests/ppc64/power_ISA2_05.stderr.exp b/memcheck/tests/ppc64/power_ISA2_05.stderr.exp new file mode 100644 index 0000000000..c22dd7f4c0 --- /dev/null +++ b/memcheck/tests/ppc64/power_ISA2_05.stderr.exp @@ -0,0 +1,10 @@ + + +HEAP SUMMARY: + in use at exit: 0 bytes in 0 blocks + total heap usage: 0 allocs, 0 frees, 0 bytes allocated + +For a detailed leak analysis, rerun with: --leak-check=full + +For counts of detected and suppressed errors, rerun with: -v +ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from 0) diff --git a/memcheck/tests/ppc64/power_ISA2_05.stdout.exp b/memcheck/tests/ppc64/power_ISA2_05.stdout.exp new file mode 100644 index 0000000000..b5a7458d2d --- /dev/null +++ b/memcheck/tests/ppc64/power_ISA2_05.stdout.exp @@ -0,0 +1,123 @@ +lwarx => 0 +ldarx => bad0beef +fcpsgn sign=10.101010, base=11.111111 => 11.111111 +fcpsgn sign=10.101010, base=-0.000000 => 0.000000 +fcpsgn sign=10.101010, base=0.000000 => 0.000000 +fcpsgn sign=10.101010, base=-11.111111 => 11.111111 +fcpsgn sign=-0.000000, base=11.111111 => -11.111111 +fcpsgn sign=-0.000000, base=-0.000000 => -0.000000 +fcpsgn sign=-0.000000, base=0.000000 => -0.000000 +fcpsgn sign=-0.000000, base=-11.111111 => -11.111111 +fcpsgn sign=0.000000, base=11.111111 => 11.111111 +fcpsgn sign=0.000000, base=-0.000000 => 0.000000 +fcpsgn sign=0.000000, base=0.000000 => 0.000000 +fcpsgn sign=0.000000, base=-11.111111 => 11.111111 +fcpsgn sign=-10.101010, base=11.111111 => -11.111111 +fcpsgn sign=-10.101010, base=-0.000000 => -0.000000 +fcpsgn sign=-10.101010, base=0.000000 => -0.000000 +fcpsgn sign=-10.101010, base=-11.111111 => -11.111111 +lfdp (-1024.000000, 1025.000000) => F_hi=-1024.000000, F_lo=1025.000000 +stfdp (2.204800, -4.102400) => F_hi=2.204800, F_lo=-4.102400 +lfdpx (2.204800, -4.102400) => F_hi=2.204800, F_lo=-4.102400 +stfdpx (2.204800, -4.102400) => F_hi=2.204800, F_lo=-4.102400 +lfiwax (-1024.000000) => FRT=(ffffffff, c0900000) +prtyd (0) => parity=0 +prtyw (0) => parity=0 +prtyd (1) => parity=1 +prtyw (1) => parity=1 +prtyd (2) => parity=0 +prtyw (2) => parity=0 +prtyd (3) => parity=1 +prtyw (3) => parity=1 +prtyd (4) => parity=0 +prtyw (4) => parity=0 +prtyd (5) => parity=1 +prtyw (5) => parity=1 +prtyd (6) => parity=0 +prtyw (6) => parity=0 +prtyd (7) => parity=1 +prtyw (7) => parity=1 +prtyd (8) => parity=0 +prtyw (8) => parity=0 +prtyd (9) => parity=1 +prtyw (9) => parity=1 +prtyd (a) => parity=0 +prtyw (a) => parity=0 +prtyd (b) => parity=1 +prtyw (b) => parity=1 +prtyd (c) => parity=0 +prtyw (c) => parity=0 +prtyd (d) => parity=1 +prtyw (d) => parity=1 +prtyd (e) => parity=0 +prtyw (e) => parity=0 +prtyd (f) => parity=1 +prtyw (f) => parity=1 +prtyd (10) => parity=0 +prtyw (10) => parity=0 +prtyd (11) => parity=1 +prtyw (11) => parity=1 +prtyd (12) => parity=0 +prtyw (12) => parity=0 +prtyd (13) => parity=1 +prtyw (13) => parity=1 +prtyd (14) => parity=0 +prtyw (14) => parity=0 +prtyd (15) => parity=1 +prtyw (15) => parity=1 +prtyd (16) => parity=0 +prtyw (16) => parity=0 +prtyd (17) => parity=1 +prtyw (17) => parity=1 +prtyd (18) => parity=0 +prtyw (18) => parity=0 +prtyd (19) => parity=1 +prtyw (19) => parity=1 +prtyd (1a) => parity=0 +prtyw (1a) => parity=0 +prtyd (1b) => parity=1 +prtyw (1b) => parity=1 +prtyd (1c) => parity=0 +prtyw (1c) => parity=0 +prtyd (1d) => parity=1 +prtyw (1d) => parity=1 +prtyd (1e) => parity=0 +prtyw (1e) => parity=0 +prtyd (1f) => parity=1 +prtyw (1f) => parity=1 +prtyd (20) => parity=0 +prtyw (20) => parity=0 +prtyd (21) => parity=1 +prtyw (21) => parity=1 +prtyd (22) => parity=0 +prtyw (22) => parity=0 +prtyd (23) => parity=1 +prtyw (23) => parity=1 +prtyd (24) => parity=0 +prtyw (24) => parity=0 +prtyd (25) => parity=1 +prtyw (25) => parity=1 +prtyd (26) => parity=0 +prtyw (26) => parity=0 +prtyd (27) => parity=1 +prtyw (27) => parity=1 +prtyd (28) => parity=0 +prtyw (28) => parity=0 +prtyd (29) => parity=1 +prtyw (29) => parity=1 +prtyd (2a) => parity=0 +prtyw (2a) => parity=0 +prtyd (2b) => parity=1 +prtyw (2b) => parity=1 +prtyd (2c) => parity=0 +prtyw (2c) => parity=0 +prtyd (2d) => parity=1 +prtyw (2d) => parity=1 +prtyd (2e) => parity=0 +prtyw (2e) => parity=0 +prtyd (2f) => parity=1 +prtyw (2f) => parity=1 +prtyd (30) => parity=0 +prtyw (30) => parity=0 +prtyd (31) => parity=1 +prtyw (31) => parity=1 diff --git a/memcheck/tests/ppc64/power_ISA2_05.vgtest b/memcheck/tests/ppc64/power_ISA2_05.vgtest new file mode 100644 index 0000000000..7f0006a86d --- /dev/null +++ b/memcheck/tests/ppc64/power_ISA2_05.vgtest @@ -0,0 +1,2 @@ +prog: power_ISA2_05 +vgopts: --workaround-gcc296-bugs=yes diff --git a/none/tests/ppc32/Makefile.am b/none/tests/ppc32/Makefile.am index 1f564fb57c..d3da324c38 100644 --- a/none/tests/ppc32/Makefile.am +++ b/none/tests/ppc32/Makefile.am @@ -21,18 +21,28 @@ EXTRA_DIST = \ testVMX.stderr.exp testVMX.stdout.exp testVMX.vgtest \ twi.stderr.exp twi.stdout.exp twi.vgtest \ tw.stderr.exp tw.stdout.exp tw.vgtest \ - xlc_dbl_u32.stderr.exp xlc_dbl_u32.stdout.exp xlc_dbl_u32.vgtest + xlc_dbl_u32.stderr.exp xlc_dbl_u32.stdout.exp xlc_dbl_u32.vgtest \ + power5+_round.stderr.exp power5+_round.stdout.exp power5+_round.vgtest \ + power6_bcmp.stderr.exp power6_bcmp.stdout.exp power6_bcmp.vgtest check_PROGRAMS = \ bug129390-ppc32 \ bug139050-ppc32 \ ldstrev lsw jm-insns mftocrf mcrfs round test_fx test_gx \ - testVMX twi tw xlc_dbl_u32 + testVMX twi tw xlc_dbl_u32 power5+_round power6_bcmp AM_CFLAGS += @FLAG_M32@ AM_CXXFLAGS += @FLAG_M32@ AM_CCASFLAGS += @FLAG_M32@ -jm_insns_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames -maltivec @FLAG_M32@ +if HAS_ALTIVEC +ALTIVEC_FLAG = -DHAS_ALTIVEC +else +ALTIVEC_FLAG = +endif + +jm_insns_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames -maltivec \ + @FLAG_M32@ $(ALTIVEC_FLAG) + testVMX_CFLAGS = $(AM_CFLAGS) -O -g -Wall -maltivec -mabi=altivec -DALTIVEC \ -DGCC_COMPILER @FLAG_M32@ diff --git a/none/tests/ppc32/bug129390-ppc32.vgtest b/none/tests/ppc32/bug129390-ppc32.vgtest index a4fb6ba679..d7d05b3c76 100644 --- a/none/tests/ppc32/bug129390-ppc32.vgtest +++ b/none/tests/ppc32/bug129390-ppc32.vgtest @@ -1,2 +1,3 @@ +prereq: ../../../tests/check_vmx_cap prog: bug129390-ppc32 vgopts: -q diff --git a/none/tests/ppc32/jm-insns.c b/none/tests/ppc32/jm-insns.c index d66462e7a8..72556f3672 100644 --- a/none/tests/ppc32/jm-insns.c +++ b/none/tests/ppc32/jm-insns.c @@ -211,10 +211,10 @@ typedef uint64_t HWord_t; /* XXXX these must all be callee-save regs! */ -register double f14 __asm__ ("f14"); -register double f15 __asm__ ("f15"); -register double f16 __asm__ ("f16"); -register double f17 __asm__ ("f17"); +register double f14 __asm__ ("fr14"); +register double f15 __asm__ ("fr15"); +register double f16 __asm__ ("fr16"); +register double f17 __asm__ ("fr17"); register HWord_t r14 __asm__ ("r14"); register HWord_t r15 __asm__ ("r15"); register HWord_t r16 __asm__ ("r16"); diff --git a/none/tests/ppc32/jm-vmx.vgtest b/none/tests/ppc32/jm-vmx.vgtest index 0f32c0d2b2..183536b562 100644 --- a/none/tests/ppc32/jm-vmx.vgtest +++ b/none/tests/ppc32/jm-vmx.vgtest @@ -1 +1,2 @@ +prereq: ../../../tests/check_vmx_cap prog: jm-insns -a diff --git a/none/tests/ppc32/power5+_round.c b/none/tests/ppc32/power5+_round.c new file mode 100644 index 0000000000..d6f6bc3206 --- /dev/null +++ b/none/tests/ppc32/power5+_round.c @@ -0,0 +1,168 @@ +/* Copyright (C) 2007 IBM + + Author: Pete Eberlein eberlein@us.ibm.com + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + 02111-1307, USA. + + The GNU General Public License is contained in the file COPYING. +*/ + + + +#include +#include +#include + +#define POS_NORMAL 0x4000 +#define NEG_NORMAL 0x8000 +#define POS_INF 0x5000 +#define NEG_INF 0x9000 +#define POS_ZERO 0x2000 +#define NEG_ZERO 0x12000 +#define POS_DENORMAL 0x14000 +#define NEG_DENORMAL 0x18000 +#define NAN 0x11000 +#define FPRF_MASK 0x1F000 + + +int main(int argc, char *argv[]) +{ + + double inf, neg0, nan; + union { + double d; + struct { + unsigned int dummy, dummy2:15, fprf:17; + }; + } fpscr; + + inf = strtod("inf", NULL); + neg0 = strtod("-0", NULL); + nan = strtod("nan", NULL); + + + /* This set is disabled until fprf is implemented. */ + if (0) { + double set[] = { inf, 1.5, 0, neg0, -1.5, -inf, nan }; + int i, j, fprf; + for (i = 0; i < 7; ++i) { + for (j = 0; j < 7; ++j) { + asm("fcmpu 1, %1, %2\n\t" "mffs %0\n":"=f"(fpscr.d) + : "f"(set[i]), "f"(set[j]) + ); + + if (i == 6 || j == 6) { + fprf = 0x1000; // Unordered + } else if (i == j || (i == 2 && j == 3) || (i == 3 && j == 2)) { + fprf = 0x2000; // Equal + } else if (i < j) { + fprf = 0x4000; // Greater Than + } else if (i > j) { + fprf = 0x8000; // Less Than + } + + printf("fcmpu\t%.1f\t%.1f\t%x\t%s\n", set[i], set[j], + fpscr.fprf, fpscr.fprf == fprf ? "PASS" : "FAIL"); + } + } + } + + { + double set[] = { inf, 1.9, 1.1, 0, neg0, -1.1, -1.9, -inf, nan }; + double frin[] = { inf, 2.0, 1.0, 0, neg0, -1.0, -2.0, -inf, nan }; + double friz[] = { inf, 1.0, 1.0, 0, neg0, -1.0, -1.0, -inf, nan }; + double frip[] = { inf, 2.0, 2.0, 0, neg0, -1.0, -1.0, -inf, nan }; + double frim[] = { inf, 1.0, 1.0, 0, neg0, -2.0, -2.0, -inf, nan }; + int fprf[] = { POS_INF, POS_NORMAL, POS_NORMAL, POS_ZERO, NEG_ZERO, + NEG_NORMAL, NEG_NORMAL, NEG_INF, NAN + }; + double set2[] = { 0.9, 0.1, -0.1, -0.9, 1e-40, -1e-40 }; + double frin2[] = { 1.0, 0.0, -0.0, -1.0, 0.0, -0.0 }; + int frin2rf[] = + { POS_NORMAL, POS_ZERO, NEG_ZERO, NEG_NORMAL, POS_ZERO, + NEG_ZERO }; + double friz2[] = { 0.0, 0.0, -0.0, -0.0, 0.0, -0.0 }; + int friz2rf[] = + { POS_ZERO, POS_ZERO, NEG_ZERO, NEG_ZERO, POS_ZERO, NEG_ZERO }; + double frip2[] = { 1.0, 1.0, -0.0, -0.0, 1.0, -0.0 }; + int frip2rf[] = + { POS_NORMAL, POS_NORMAL, NEG_ZERO, NEG_ZERO, POS_NORMAL, + NEG_ZERO }; + double frim2[] = { 0.0, 0.0, -1.0, -1.0, 0.0, -1.0 }; + int frim2rf[] = + { POS_ZERO, POS_ZERO, NEG_NORMAL, NEG_NORMAL, POS_ZERO, + NEG_NORMAL }; + double ret; + int i; + +#define DO_TEST(op,in,out,rf) for (i=0; i +#include +#include + +#define CMPB(result,a,b) \ + asm __volatile ("cmpb %0, %1, %2\n" : "=r"(result) : "r"(a), "r"(b)) + + +int main(int argc, char *argv[]) +{ + int i, j, k; + long mask; + for (i = 1; i < 16; i++) { + mask = 0; + if (i & 1) + mask += 0xff; + if (i & 2) + mask += 0xff00; + if (i & 4) + mask += 0xff0000; + if (i & 8) + mask += 0xff000000; + + for (j = 0; j < 256; j++) + for (k = 0; k < 256; k++) + if (j != k) { + + long a, b, result; + a = (mask & (j * 0x1010101)) + ((~mask) & (k * 0x1010101)); + b = j * 0x1010101; + CMPB(result, a, b); + if (result != mask) + printf("%llx %llx %llx %llx\n", + (unsigned long long) mask, (unsigned long long) a, + (unsigned long long) b, + (unsigned long long) result); + exit(1); + } + + } + + return 0; +} diff --git a/none/tests/ppc32/power6_bcmp.stderr.exp b/none/tests/ppc32/power6_bcmp.stderr.exp new file mode 100644 index 0000000000..139597f9cb --- /dev/null +++ b/none/tests/ppc32/power6_bcmp.stderr.exp @@ -0,0 +1,2 @@ + + diff --git a/none/tests/ppc32/power6_bcmp.vgtest b/none/tests/ppc32/power6_bcmp.vgtest new file mode 100644 index 0000000000..28146c0ff6 --- /dev/null +++ b/none/tests/ppc32/power6_bcmp.vgtest @@ -0,0 +1 @@ +prog: power6_bcmp diff --git a/none/tests/ppc32/testVMX.vgtest b/none/tests/ppc32/testVMX.vgtest index 7c51503139..81c59f2012 100644 --- a/none/tests/ppc32/testVMX.vgtest +++ b/none/tests/ppc32/testVMX.vgtest @@ -1 +1,2 @@ +prereq: ../../../tests/check_vmx_cap prog: testVMX diff --git a/none/tests/ppc64/Makefile.am b/none/tests/ppc64/Makefile.am index 5d8b08d77c..fdd515a9fc 100644 --- a/none/tests/ppc64/Makefile.am +++ b/none/tests/ppc64/Makefile.am @@ -11,13 +11,23 @@ EXTRA_DIST = \ std_reg_imm.vgtest std_reg_imm.stderr.exp std_reg_imm.stdout.exp \ round.stderr.exp round.stdout.exp round.vgtest \ twi_tdi.stderr.exp twi_tdi.stdout.exp twi_tdi.vgtest \ - tw_td.stderr.exp tw_td.stdout.exp tw_td.vgtest + tw_td.stderr.exp tw_td.stdout.exp tw_td.vgtest \ + power6_bcmp.stderr.exp power6_bcmp.stdout.exp power6_bcmp.vgtest \ + power6_mf_gpr.stderr.exp power6_mf_gpr.stdout.exp power6_mf_gpr.vgtest check_PROGRAMS = \ - jm-insns lsw round std_reg_imm twi_tdi tw_td + jm-insns lsw round std_reg_imm twi_tdi tw_td power6_bcmp power6_mf_gpr AM_CFLAGS += @FLAG_M64@ AM_CXXFLAGS += @FLAG_M64@ AM_CCASFLAGS += @FLAG_M64@ -jm_insns_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames -maltivec @FLAG_M64@ +if HAS_ALTIVEC +ALTIVEC_FLAG = -DHAS_ALTIVEC +else +ALTIVEC_FLAG = +endif + +jm_insns_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames -maltivec \ + @FLAG_M64@ $(ALTIVEC_FLAG) + diff --git a/none/tests/ppc64/jm-vmx.vgtest b/none/tests/ppc64/jm-vmx.vgtest index 0f32c0d2b2..183536b562 100644 --- a/none/tests/ppc64/jm-vmx.vgtest +++ b/none/tests/ppc64/jm-vmx.vgtest @@ -1 +1,2 @@ +prereq: ../../../tests/check_vmx_cap prog: jm-insns -a diff --git a/none/tests/ppc64/power6_bcmp.c b/none/tests/ppc64/power6_bcmp.c new file mode 100644 index 0000000000..d0a09fbe0d --- /dev/null +++ b/none/tests/ppc64/power6_bcmp.c @@ -0,0 +1,72 @@ +/* Copyright (C) 2007 IBM + + Author: Pete Eberlein eberlein@us.ibm.com + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + 02111-1307, USA. + + The GNU General Public License is contained in the file COPYING. +*/ + + +#include +#include +#include + +#define CMPB(result,a,b) \ + asm ("cmpb %0, %1, %2\n" : "=r"(result) : "r"(a), "r"(b)) + + +int main(int argc, char *argv[]) +{ + int i, j, k; + unsigned long mask; + for (i = 1; i < 256; i++) { + mask = 0; + if (i & 1) + mask += 0xff; + if (i & 2) + mask += 0xff00; + if (i & 4) + mask += 0xff0000; + if (i & 8) + mask += 0xff000000; + if (i & 16) + mask += 0xff00000000; + if (i & 32) + mask += 0xff0000000000; + if (i & 64) + mask += 0xff000000000000; + if (i & 128) + mask += 0xff00000000000000; + + for (j = 0; j < 256; j++) + for (k = 0; k < 256; k++) + if (j != k) { + + unsigned long a, b, result; + a = (mask & (j * 0x101010101010101)) + + ((~mask) & (k * 0x101010101010101)); + b = j * 0x101010101010101; + CMPB(result, a, b); + if (result != mask) + printf("%8lx %8lx %8lx %8lx\n", mask, a, b, result); + exit(1); + } + + } + + return 0; +} diff --git a/none/tests/ppc64/power6_bcmp.stderr.exp b/none/tests/ppc64/power6_bcmp.stderr.exp new file mode 100644 index 0000000000..139597f9cb --- /dev/null +++ b/none/tests/ppc64/power6_bcmp.stderr.exp @@ -0,0 +1,2 @@ + + diff --git a/none/tests/ppc64/power6_bcmp.vgtest b/none/tests/ppc64/power6_bcmp.vgtest new file mode 100644 index 0000000000..28146c0ff6 --- /dev/null +++ b/none/tests/ppc64/power6_bcmp.vgtest @@ -0,0 +1 @@ +prog: power6_bcmp diff --git a/none/tests/ppc64/power6_mf_gpr.c b/none/tests/ppc64/power6_mf_gpr.c new file mode 100644 index 0000000000..ba4bf4d7cc --- /dev/null +++ b/none/tests/ppc64/power6_mf_gpr.c @@ -0,0 +1,49 @@ +/* Copyright (C) 2007 IBM + + Author: Pete Eberlein eberlein@us.ibm.com + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + 02111-1307, USA. + + The GNU General Public License is contained in the file COPYING. +*/ + +#include +#include + + + +int main(int argc, char *argv[]) +{ + + long i; + double f; + + i = 0; + f = 100.0; + + printf("%lx %f\n", i, f); + + asm("mftgpr %0, %1\n": "=r"(i):"f"(f)); + + f = 0.0; + printf("%lx %f\n", i, f); + + asm("mffgpr %0, %1\n": "=f"(f):"r"(i)); + + printf("%lx %f\n", i, f); + + return 0; +} diff --git a/none/tests/ppc64/power6_mf_gpr.stderr.exp b/none/tests/ppc64/power6_mf_gpr.stderr.exp new file mode 100644 index 0000000000..139597f9cb --- /dev/null +++ b/none/tests/ppc64/power6_mf_gpr.stderr.exp @@ -0,0 +1,2 @@ + + diff --git a/none/tests/ppc64/power6_mf_gpr.stdout.exp b/none/tests/ppc64/power6_mf_gpr.stdout.exp new file mode 100644 index 0000000000..7bc827dd22 --- /dev/null +++ b/none/tests/ppc64/power6_mf_gpr.stdout.exp @@ -0,0 +1,3 @@ +0 100.000000 +4059000000000000 0.000000 +4059000000000000 100.000000 diff --git a/none/tests/ppc64/power6_mf_gpr.vgtest b/none/tests/ppc64/power6_mf_gpr.vgtest new file mode 100644 index 0000000000..5868fe66ee --- /dev/null +++ b/none/tests/ppc64/power6_mf_gpr.vgtest @@ -0,0 +1 @@ +prog: power6_mf_gpr diff --git a/tests/Makefile.am b/tests/Makefile.am index 44e2636a4c..fe314897b3 100644 --- a/tests/Makefile.am +++ b/tests/Makefile.am @@ -2,6 +2,7 @@ include $(top_srcdir)/Makefile.tool-tests.am dist_noinst_SCRIPTS = \ + check_vmx_cap \ filter_addresses \ filter_discards \ filter_libc \ diff --git a/tests/check_vmx_cap b/tests/check_vmx_cap new file mode 100755 index 0000000000..12e5f68ec6 --- /dev/null +++ b/tests/check_vmx_cap @@ -0,0 +1,11 @@ +#!/bin/sh + +# We use this script to check whether or not the processor supports VMX (aka "Altivec"). + +LD_SHOW_AUXV=1 /bin/true | grep altivec > /dev/null 2>&1 +if [ "$?" -ne "0" ]; then + exit 1 +else + exit 0 +fi +