From: Petar Jovanovic <mips32r2@gmail.com>
Date: Tue, 25 Apr 2017 14:40:54 +0000 (+0000)
Subject: mips: limit cvt.s.l instruction translation to fp_mode64
X-Git-Tag: svn/VALGRIND_3_13_0^2~30
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=92adc1192e22c6f786d40245b9ee21b98ec090c6;p=thirdparty%2Fvalgrind.git

mips: limit cvt.s.l instruction translation to fp_mode64

The documentation says:
"For CVT.S.L, the result of this instruction is UNPREDICTABLE if the
processor is executing in the FR=0 32-bit FPU register model; it is
predictable if executing on a 64-bit FPU in the FR=1 mode, but not with
FR=0, and not on a 32-bit FPU."

Hence the fix.



git-svn-id: svn://svn.valgrind.org/vex/trunk@3354
---

diff --git a/VEX/priv/guest_mips_toIR.c b/VEX/priv/guest_mips_toIR.c
index 0a63875cbe..c10693c49f 100644
--- a/VEX/priv/guest_mips_toIR.c
+++ b/VEX/priv/guest_mips_toIR.c
@@ -13090,12 +13090,16 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
 
                   case 0x15:  /* L */
                      DIP("cvt.s.l %u, %u", fd, fs);
-                     calculateFCSR(fs, 0, CVTSL, False, 1);
-                     t0 = newTemp(Ity_I64);
-                     assign(t0, unop(Iop_ReinterpF64asI64, getFReg(fs)));
+                     if (fp_mode64) {
+                        calculateFCSR(fs, 0, CVTSL, False, 1);
+                        t0 = newTemp(Ity_I64);
+                        assign(t0, unop(Iop_ReinterpF64asI64, getFReg(fs)));
 
-                     putFReg(fd, mkWidenFromF32(tyF, binop(Iop_I64StoF32,
-                                 get_IR_roundingmode(), mkexpr(t0))));
+                        putFReg(fd, mkWidenFromF32(tyF, binop(Iop_I64StoF32,
+                                    get_IR_roundingmode(), mkexpr(t0))));
+                     } else {
+                        ILLEGAL_INSTRUCTON;
+                     }
                      break;
 
                   default: