From: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date: Thu, 31 Mar 2016 16:33:51 +0000 (+0000)
Subject: [ARM] Fix sync.md ldrd output template for non-unified syntax
X-Git-Tag: releases/gcc-4.9.4~246
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=92b1f12422854c2e9eef8d12694de9b664dcc2a8;p=thirdparty%2Fgcc.git

[ARM] Fix sync.md ldrd output template for non-unified syntax

	* config/arm/sync.md (arm_atomic_loaddi2_ldrd): Fix output template
	for non-unified syntax.

	* gcc.target/arm/atomic_loaddi_relaxed_cond.c: New test.

From-SVN: r234642
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 2d2631c82dba..a0f3186a4f7c 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2016-03-31  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* config/arm/sync.md (arm_atomic_loaddi2_ldrd): Fix output template
+	for non-unified syntax.
+
 2016-03-31  Jakub Jelinek  <jakub@redhat.com>
 
 	PR rtl-optimization/70460
diff --git a/gcc/config/arm/sync.md b/gcc/config/arm/sync.md
index 5218ea3b8cbf..773b4b45fa48 100644
--- a/gcc/config/arm/sync.md
+++ b/gcc/config/arm/sync.md
@@ -111,7 +111,7 @@
 	[(match_operand:DI 1 "arm_sync_memory_operand" "Q")]
 	  VUNSPEC_LDRD_ATOMIC))]
   "ARM_DOUBLEWORD_ALIGN && TARGET_HAVE_LPAE"
-  "ldrd%?\t%0, %H0, %C1"
+  "ldr%(d%)\t%0, %H0, %C1"
   [(set_attr "predicable" "yes")
    (set_attr "predicable_short_it" "no")])
 
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index c440eae34476..52bdf72a3df5 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2016-03-31  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* gcc.target/arm/atomic_loaddi_relaxed_cond.c: New test.
+
 2016-03-31  Jakub Jelinek  <jakub@redhat.com>
 
 	PR rtl-optimization/70460
diff --git a/gcc/testsuite/gcc.target/arm/atomic_loaddi_relaxed_cond.c b/gcc/testsuite/gcc.target/arm/atomic_loaddi_relaxed_cond.c
new file mode 100644
index 000000000000..d69775150813
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/atomic_loaddi_relaxed_cond.c
@@ -0,0 +1,20 @@
+/* { dg-do assemble } */
+/* { dg-options "-std=c11 -O" } */
+/* { dg-require-effective-target arm_arch_v8a_ok } */
+/* { dg-add-options arm_arch_v8a } */
+
+/* Check that if we conditionalise the atomic load we put the condition
+   code in the right place to create valid assembly.  */
+
+#include <stdatomic.h>
+
+atomic_ullong foo;
+int glob;
+
+int
+main (int argc, char *argv[])
+{
+  if (argc > 2)
+    atomic_load_explicit (&foo, memory_order_relaxed);
+  return glob;
+}