From: Greg Kroah-Hartman Date: Wed, 30 Jul 2025 08:00:20 +0000 (+0200) Subject: 6.12-stable patches X-Git-Tag: v6.6.101~7 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=92d94ca84c75738e5d0dbf19cc5971bb93a65cd2;p=thirdparty%2Fkernel%2Fstable-queue.git 6.12-stable patches added patches: alsa-hda-add-missing-nvidia-hda-codec-ids.patch alsa-hda-tegra-add-tegra264-support.patch drm-i915-dp-fix-2.7-gbps-dp_link_bw-value-on-g4x.patch revert-drm-xe-devcoredump-update-handling-of-xe_force_wake_get-return.patch revert-drm-xe-forcewake-add-a-helper-xe_force_wake_ref_has_domain.patch revert-drm-xe-gt-update-handling-of-xe_force_wake_get-return.patch revert-drm-xe-tests-mocs-update-xe_force_wake_get-return-handling.patch --- diff --git a/queue-6.12/alsa-hda-add-missing-nvidia-hda-codec-ids.patch b/queue-6.12/alsa-hda-add-missing-nvidia-hda-codec-ids.patch new file mode 100644 index 0000000000..ab17ef1a36 --- /dev/null +++ b/queue-6.12/alsa-hda-add-missing-nvidia-hda-codec-ids.patch @@ -0,0 +1,67 @@ +From e0a911ac86857a73182edde9e50d9b4b949b7f01 Mon Sep 17 00:00:00 2001 +From: Daniel Dadap +Date: Thu, 26 Jun 2025 16:16:30 -0500 +Subject: ALSA: hda: Add missing NVIDIA HDA codec IDs + +From: Daniel Dadap + +commit e0a911ac86857a73182edde9e50d9b4b949b7f01 upstream. + +Add codec IDs for several NVIDIA products with HDA controllers to the +snd_hda_id_hdmi[] patch table. + +Signed-off-by: Daniel Dadap +Cc: +Link: https://patch.msgid.link/aF24rqwMKFWoHu12@ddadap-lakeline.nvidia.com +Signed-off-by: Takashi Iwai +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + sound/pci/hda/patch_hdmi.c | 19 +++++++++++++++++++ + 1 file changed, 19 insertions(+) + +--- a/sound/pci/hda/patch_hdmi.c ++++ b/sound/pci/hda/patch_hdmi.c +@@ -4551,7 +4551,9 @@ HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HD + HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi), + HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi), + HDA_CODEC_ENTRY(0x10de0031, "Tegra234 HDMI/DP", patch_tegra234_hdmi), ++HDA_CODEC_ENTRY(0x10de0033, "SoC 33 HDMI/DP", patch_tegra234_hdmi), + HDA_CODEC_ENTRY(0x10de0034, "Tegra264 HDMI/DP", patch_tegra234_hdmi), ++HDA_CODEC_ENTRY(0x10de0035, "SoC 35 HDMI/DP", patch_tegra234_hdmi), + HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi), + HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi), + HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi), +@@ -4590,15 +4592,32 @@ HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI + HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi), + HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi), + HDA_CODEC_ENTRY(0x10de009a, "GPU 9a HDMI/DP", patch_nvhdmi), ++HDA_CODEC_ENTRY(0x10de009b, "GPU 9b HDMI/DP", patch_nvhdmi), ++HDA_CODEC_ENTRY(0x10de009c, "GPU 9c HDMI/DP", patch_nvhdmi), + HDA_CODEC_ENTRY(0x10de009d, "GPU 9d HDMI/DP", patch_nvhdmi), + HDA_CODEC_ENTRY(0x10de009e, "GPU 9e HDMI/DP", patch_nvhdmi), + HDA_CODEC_ENTRY(0x10de009f, "GPU 9f HDMI/DP", patch_nvhdmi), + HDA_CODEC_ENTRY(0x10de00a0, "GPU a0 HDMI/DP", patch_nvhdmi), ++HDA_CODEC_ENTRY(0x10de00a1, "GPU a1 HDMI/DP", patch_nvhdmi), + HDA_CODEC_ENTRY(0x10de00a3, "GPU a3 HDMI/DP", patch_nvhdmi), + HDA_CODEC_ENTRY(0x10de00a4, "GPU a4 HDMI/DP", patch_nvhdmi), + HDA_CODEC_ENTRY(0x10de00a5, "GPU a5 HDMI/DP", patch_nvhdmi), + HDA_CODEC_ENTRY(0x10de00a6, "GPU a6 HDMI/DP", patch_nvhdmi), + HDA_CODEC_ENTRY(0x10de00a7, "GPU a7 HDMI/DP", patch_nvhdmi), ++HDA_CODEC_ENTRY(0x10de00a8, "GPU a8 HDMI/DP", patch_nvhdmi), ++HDA_CODEC_ENTRY(0x10de00a9, "GPU a9 HDMI/DP", patch_nvhdmi), ++HDA_CODEC_ENTRY(0x10de00aa, "GPU aa HDMI/DP", patch_nvhdmi), ++HDA_CODEC_ENTRY(0x10de00ab, "GPU ab HDMI/DP", patch_nvhdmi), ++HDA_CODEC_ENTRY(0x10de00ad, "GPU ad HDMI/DP", patch_nvhdmi), ++HDA_CODEC_ENTRY(0x10de00ae, "GPU ae HDMI/DP", patch_nvhdmi), ++HDA_CODEC_ENTRY(0x10de00af, "GPU af HDMI/DP", patch_nvhdmi), ++HDA_CODEC_ENTRY(0x10de00b0, "GPU b0 HDMI/DP", patch_nvhdmi), ++HDA_CODEC_ENTRY(0x10de00b1, "GPU b1 HDMI/DP", patch_nvhdmi), ++HDA_CODEC_ENTRY(0x10de00c0, "GPU c0 HDMI/DP", patch_nvhdmi), ++HDA_CODEC_ENTRY(0x10de00c1, "GPU c1 HDMI/DP", patch_nvhdmi), ++HDA_CODEC_ENTRY(0x10de00c3, "GPU c3 HDMI/DP", patch_nvhdmi), ++HDA_CODEC_ENTRY(0x10de00c4, "GPU c4 HDMI/DP", patch_nvhdmi), ++HDA_CODEC_ENTRY(0x10de00c5, "GPU c5 HDMI/DP", patch_nvhdmi), + HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch), + HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch), + HDA_CODEC_ENTRY(0x67663d82, "Arise 82 HDMI/DP", patch_gf_hdmi), diff --git a/queue-6.12/alsa-hda-tegra-add-tegra264-support.patch b/queue-6.12/alsa-hda-tegra-add-tegra264-support.patch new file mode 100644 index 0000000000..258f69062b --- /dev/null +++ b/queue-6.12/alsa-hda-tegra-add-tegra264-support.patch @@ -0,0 +1,161 @@ +From 1c4193917eb3279788968639f24d72ffeebdec6b Mon Sep 17 00:00:00 2001 +From: Mohan Kumar D +Date: Mon, 12 May 2025 06:42:58 +0000 +Subject: ALSA: hda/tegra: Add Tegra264 support + +From: Mohan Kumar D + +commit 1c4193917eb3279788968639f24d72ffeebdec6b upstream. + +Update HDA driver to support Tegra264 differences from legacy HDA, +which includes: clocks/resets, always power on, and hardware-managed +FPCI/IPFS initialization. The driver retrieves this chip-specific +information from soc_data. + +Signed-off-by: Mohan Kumar D +Signed-off-by: Sheetal +Signed-off-by: Takashi Iwai +Link: https://patch.msgid.link/20250512064258.1028331-4-sheetal@nvidia.com +Stable-dep-of: e0a911ac8685 ("ALSA: hda: Add missing NVIDIA HDA codec IDs") +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + sound/pci/hda/hda_tegra.c | 51 +++++++++++++++++++++++++++++++++++++++------ + sound/pci/hda/patch_hdmi.c | 1 + 2 files changed, 46 insertions(+), 6 deletions(-) + +--- a/sound/pci/hda/hda_tegra.c ++++ b/sound/pci/hda/hda_tegra.c +@@ -72,6 +72,10 @@ + struct hda_tegra_soc { + bool has_hda2codec_2x_reset; + bool has_hda2hdmi; ++ bool has_hda2codec_2x; ++ bool input_stream; ++ bool always_on; ++ bool requires_init; + }; + + struct hda_tegra { +@@ -187,7 +191,9 @@ static int __maybe_unused hda_tegra_runt + if (rc != 0) + return rc; + if (chip->running) { +- hda_tegra_init(hda); ++ if (hda->soc->requires_init) ++ hda_tegra_init(hda); ++ + azx_init_chip(chip, 1); + /* disable controller wake up event*/ + azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & +@@ -252,7 +258,8 @@ static int hda_tegra_init_chip(struct az + bus->remap_addr = hda->regs + HDA_BAR0; + bus->addr = res->start + HDA_BAR0; + +- hda_tegra_init(hda); ++ if (hda->soc->requires_init) ++ hda_tegra_init(hda); + + return 0; + } +@@ -325,7 +332,7 @@ static int hda_tegra_first_init(struct a + * starts with offset 0 which is wrong as HW register for output stream + * offset starts with 4. + */ +- if (of_device_is_compatible(np, "nvidia,tegra234-hda")) ++ if (!hda->soc->input_stream) + chip->capture_streams = 4; + + chip->playback_streams = (gcap >> 12) & 0x0f; +@@ -421,7 +428,6 @@ static int hda_tegra_create(struct snd_c + chip->driver_caps = driver_caps; + chip->driver_type = driver_caps & 0xff; + chip->dev_index = 0; +- chip->jackpoll_interval = msecs_to_jiffies(5000); + INIT_LIST_HEAD(&chip->pcm_list); + + chip->codec_probe_mask = -1; +@@ -438,7 +444,16 @@ static int hda_tegra_create(struct snd_c + chip->bus.core.sync_write = 0; + chip->bus.core.needs_damn_long_delay = 1; + chip->bus.core.aligned_mmio = 1; +- chip->bus.jackpoll_in_suspend = 1; ++ ++ /* ++ * HDA power domain and clocks are always on for Tegra264 and ++ * the jack detection logic would work always, so no need of ++ * jack polling mechanism running. ++ */ ++ if (!hda->soc->always_on) { ++ chip->jackpoll_interval = msecs_to_jiffies(5000); ++ chip->bus.jackpoll_in_suspend = 1; ++ } + + err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); + if (err < 0) { +@@ -452,22 +467,44 @@ static int hda_tegra_create(struct snd_c + static const struct hda_tegra_soc tegra30_data = { + .has_hda2codec_2x_reset = true, + .has_hda2hdmi = true, ++ .has_hda2codec_2x = true, ++ .input_stream = true, ++ .always_on = false, ++ .requires_init = true, + }; + + static const struct hda_tegra_soc tegra194_data = { + .has_hda2codec_2x_reset = false, + .has_hda2hdmi = true, ++ .has_hda2codec_2x = true, ++ .input_stream = true, ++ .always_on = false, ++ .requires_init = true, + }; + + static const struct hda_tegra_soc tegra234_data = { + .has_hda2codec_2x_reset = true, + .has_hda2hdmi = false, ++ .has_hda2codec_2x = true, ++ .input_stream = false, ++ .always_on = false, ++ .requires_init = true, ++}; ++ ++static const struct hda_tegra_soc tegra264_data = { ++ .has_hda2codec_2x_reset = true, ++ .has_hda2hdmi = false, ++ .has_hda2codec_2x = false, ++ .input_stream = false, ++ .always_on = true, ++ .requires_init = false, + }; + + static const struct of_device_id hda_tegra_match[] = { + { .compatible = "nvidia,tegra30-hda", .data = &tegra30_data }, + { .compatible = "nvidia,tegra194-hda", .data = &tegra194_data }, + { .compatible = "nvidia,tegra234-hda", .data = &tegra234_data }, ++ { .compatible = "nvidia,tegra264-hda", .data = &tegra264_data }, + {}, + }; + MODULE_DEVICE_TABLE(of, hda_tegra_match); +@@ -522,7 +559,9 @@ static int hda_tegra_probe(struct platfo + hda->clocks[hda->nclocks++].id = "hda"; + if (hda->soc->has_hda2hdmi) + hda->clocks[hda->nclocks++].id = "hda2hdmi"; +- hda->clocks[hda->nclocks++].id = "hda2codec_2x"; ++ ++ if (hda->soc->has_hda2codec_2x) ++ hda->clocks[hda->nclocks++].id = "hda2codec_2x"; + + err = devm_clk_bulk_get(&pdev->dev, hda->nclocks, hda->clocks); + if (err < 0) +--- a/sound/pci/hda/patch_hdmi.c ++++ b/sound/pci/hda/patch_hdmi.c +@@ -4551,6 +4551,7 @@ HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HD + HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi), + HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi), + HDA_CODEC_ENTRY(0x10de0031, "Tegra234 HDMI/DP", patch_tegra234_hdmi), ++HDA_CODEC_ENTRY(0x10de0034, "Tegra264 HDMI/DP", patch_tegra234_hdmi), + HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi), + HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi), + HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi), diff --git a/queue-6.12/drm-i915-dp-fix-2.7-gbps-dp_link_bw-value-on-g4x.patch b/queue-6.12/drm-i915-dp-fix-2.7-gbps-dp_link_bw-value-on-g4x.patch new file mode 100644 index 0000000000..86ede0628a --- /dev/null +++ b/queue-6.12/drm-i915-dp-fix-2.7-gbps-dp_link_bw-value-on-g4x.patch @@ -0,0 +1,59 @@ +From 9e0c433d0c05fde284025264b89eaa4ad59f0a3e Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= +Date: Thu, 10 Jul 2025 23:17:12 +0300 +Subject: drm/i915/dp: Fix 2.7 Gbps DP_LINK_BW value on g4x +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Ville Syrjälä + +commit 9e0c433d0c05fde284025264b89eaa4ad59f0a3e upstream. + +On g4x we currently use the 96MHz non-SSC refclk, which can't actually +generate an exact 2.7 Gbps link rate. In practice we end up with 2.688 +Gbps which seems to be close enough to actually work, but link training +is currently failing due to miscalculating the DP_LINK_BW value (we +calcualte it directly from port_clock which reflects the actual PLL +outpout frequency). + +Ideas how to fix this: +- nudge port_clock back up to 270000 during PLL computation/readout +- track port_clock and the nominal link rate separately so they might + differ a bit +- switch to the 100MHz refclk, but that one should be SSC so perhaps + not something we want + +While we ponder about a better solution apply some band aid to the +immediate issue of miscalculated DP_LINK_BW value. With this +I can again use 2.7 Gbps link rate on g4x. + +Cc: stable@vger.kernel.org +Fixes: 665a7b04092c ("drm/i915: Feed the DPLL output freq back into crtc_state") +Signed-off-by: Ville Syrjälä +Link: https://patchwork.freedesktop.org/patch/msgid/20250710201718.25310-2-ville.syrjala@linux.intel.com +Reviewed-by: Imre Deak +(cherry picked from commit a8b874694db5cae7baaf522756f87acd956e6e66) +Signed-off-by: Rodrigo Vivi +[ changed display->platform.g4x to IS_G4X(i915) ] +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/display/intel_dp.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/drivers/gpu/drm/i915/display/intel_dp.c ++++ b/drivers/gpu/drm/i915/display/intel_dp.c +@@ -1506,6 +1506,12 @@ int intel_dp_rate_select(struct intel_dp + void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, + u8 *link_bw, u8 *rate_select) + { ++ struct drm_i915_private *i915 = dp_to_i915(intel_dp); ++ ++ /* FIXME g4x can't generate an exact 2.7GHz with the 96MHz non-SSC refclk */ ++ if (IS_G4X(i915) && port_clock == 268800) ++ port_clock = 270000; ++ + /* eDP 1.4 rate select method. */ + if (intel_dp->use_rate_select) { + *link_bw = 0; diff --git a/queue-6.12/revert-drm-xe-devcoredump-update-handling-of-xe_force_wake_get-return.patch b/queue-6.12/revert-drm-xe-devcoredump-update-handling-of-xe_force_wake_get-return.patch new file mode 100644 index 0000000000..c1a973d62c --- /dev/null +++ b/queue-6.12/revert-drm-xe-devcoredump-update-handling-of-xe_force_wake_get-return.patch @@ -0,0 +1,88 @@ +From stable+bounces-165054-greg=kroah.com@vger.kernel.org Tue Jul 29 13:05:57 2025 +From: Tomita Moeko +Date: Tue, 29 Jul 2025 19:05:24 +0800 +Subject: Revert "drm/xe/devcoredump: Update handling of xe_force_wake_get return" +To: "Lucas De Marchi" , "Thomas Hellström" , "Rodrigo Vivi" +Cc: intel-xe@lists.freedesktop.org, stable@vger.kernel.org, Tomita Moeko , Himal Prasad Ghimiray , Nirmoy Das , Badal Nilawar +Message-ID: <20250729110525.49838-4-tomitamoeko@gmail.com> + +From: Tomita Moeko + +This reverts commit 9ffd6ec2de08ef4ac5f17f6131d1db57613493f9. + +The reverted commit updated the handling of xe_force_wake_get to match +the new "return refcounted domain mask" semantics introduced in commit +a7ddcea1f5ac ("drm/xe: Error handling in xe_force_wake_get()"). However, +that API change only exists in 6.13 and later. + +In 6.12 stable kernel, xe_force_wake_get still returns a status code. +The update incorrectly treats the return value as a mask, causing the +return value of 0 to be misinterpreted as an error + +Cc: Rodrigo Vivi +Cc: Lucas De Marchi +Cc: Himal Prasad Ghimiray +Cc: Nirmoy Das +Cc: Badal Nilawar +Acked-by: Rodrigo Vivi +Signed-off-by: Tomita Moeko +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/xe/xe_devcoredump.c | 14 ++++++-------- + 1 file changed, 6 insertions(+), 8 deletions(-) + +--- a/drivers/gpu/drm/xe/xe_devcoredump.c ++++ b/drivers/gpu/drm/xe/xe_devcoredump.c +@@ -197,7 +197,6 @@ static void xe_devcoredump_deferred_snap + struct xe_devcoredump_snapshot *ss = container_of(work, typeof(*ss), work); + struct xe_devcoredump *coredump = container_of(ss, typeof(*coredump), snapshot); + struct xe_device *xe = coredump_to_xe(coredump); +- unsigned int fw_ref; + + /* + * NB: Despite passing a GFP_ flags parameter here, more allocations are done +@@ -211,12 +210,11 @@ static void xe_devcoredump_deferred_snap + xe_pm_runtime_get(xe); + + /* keep going if fw fails as we still want to save the memory and SW data */ +- fw_ref = xe_force_wake_get(gt_to_fw(ss->gt), XE_FORCEWAKE_ALL); +- if (!xe_force_wake_ref_has_domain(fw_ref, XE_FORCEWAKE_ALL)) ++ if (xe_force_wake_get(gt_to_fw(ss->gt), XE_FORCEWAKE_ALL)) + xe_gt_info(ss->gt, "failed to get forcewake for coredump capture\n"); + xe_vm_snapshot_capture_delayed(ss->vm); + xe_guc_exec_queue_snapshot_capture_delayed(ss->ge); +- xe_force_wake_put(gt_to_fw(ss->gt), fw_ref); ++ xe_force_wake_put(gt_to_fw(ss->gt), XE_FORCEWAKE_ALL); + + xe_pm_runtime_put(xe); + +@@ -243,9 +241,8 @@ static void devcoredump_snapshot(struct + u32 width_mask = (0x1 << q->width) - 1; + const char *process_name = "no process"; + +- unsigned int fw_ref; +- bool cookie; + int i; ++ bool cookie; + + ss->snapshot_time = ktime_get_real(); + ss->boot_time = ktime_get_boottime(); +@@ -268,7 +265,8 @@ static void devcoredump_snapshot(struct + } + + /* keep going if fw fails as we still want to save the memory and SW data */ +- fw_ref = xe_force_wake_get(gt_to_fw(q->gt), XE_FORCEWAKE_ALL); ++ if (xe_force_wake_get(gt_to_fw(q->gt), XE_FORCEWAKE_ALL)) ++ xe_gt_info(ss->gt, "failed to get forcewake for coredump capture\n"); + + ss->ct = xe_guc_ct_snapshot_capture(&guc->ct, true); + ss->ge = xe_guc_exec_queue_snapshot_capture(q); +@@ -286,7 +284,7 @@ static void devcoredump_snapshot(struct + + queue_work(system_unbound_wq, &ss->work); + +- xe_force_wake_put(gt_to_fw(q->gt), fw_ref); ++ xe_force_wake_put(gt_to_fw(q->gt), XE_FORCEWAKE_ALL); + dma_fence_end_signalling(cookie); + } + diff --git a/queue-6.12/revert-drm-xe-forcewake-add-a-helper-xe_force_wake_ref_has_domain.patch b/queue-6.12/revert-drm-xe-forcewake-add-a-helper-xe_force_wake_ref_has_domain.patch new file mode 100644 index 0000000000..4768728721 --- /dev/null +++ b/queue-6.12/revert-drm-xe-forcewake-add-a-helper-xe_force_wake_ref_has_domain.patch @@ -0,0 +1,51 @@ +From stable+bounces-165055-greg=kroah.com@vger.kernel.org Tue Jul 29 13:06:06 2025 +From: Tomita Moeko +Date: Tue, 29 Jul 2025 19:05:25 +0800 +Subject: Revert "drm/xe/forcewake: Add a helper xe_force_wake_ref_has_domain()" +To: "Lucas De Marchi" , "Thomas Hellström" , "Rodrigo Vivi" +Cc: intel-xe@lists.freedesktop.org, stable@vger.kernel.org, Tomita Moeko , Michal Wajdeczko , Badal Nilawar , Himal Prasad Ghimiray +Message-ID: <20250729110525.49838-5-tomitamoeko@gmail.com> + +From: Tomita Moeko + +This reverts commit deb05f8431f31e08fd6ab99a56069fc98014dbec. + +The helper function introduced in the reverted commit is for handling +the "refcounted domain mask" introduced in commit a7ddcea1f5ac +("drm/xe: Error handling in xe_force_wake_get()"). Since that API change +only exists in 6.13 and later, this helper is unnecessary in 6.12 stable +kernel. + +Cc: Michal Wajdeczko +Cc: Badal Nilawar +Cc: Himal Prasad Ghimiray +Acked-by: Rodrigo Vivi +Signed-off-by: Tomita Moeko +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/xe/xe_force_wake.h | 16 ---------------- + 1 file changed, 16 deletions(-) + +--- a/drivers/gpu/drm/xe/xe_force_wake.h ++++ b/drivers/gpu/drm/xe/xe_force_wake.h +@@ -46,20 +46,4 @@ xe_force_wake_assert_held(struct xe_forc + xe_gt_assert(fw->gt, fw->awake_domains & domain); + } + +-/** +- * xe_force_wake_ref_has_domain - verifies if the domains are in fw_ref +- * @fw_ref : the force_wake reference +- * @domain : forcewake domain to verify +- * +- * This function confirms whether the @fw_ref includes a reference to the +- * specified @domain. +- * +- * Return: true if domain is refcounted. +- */ +-static inline bool +-xe_force_wake_ref_has_domain(unsigned int fw_ref, enum xe_force_wake_domains domain) +-{ +- return fw_ref & domain; +-} +- + #endif diff --git a/queue-6.12/revert-drm-xe-gt-update-handling-of-xe_force_wake_get-return.patch b/queue-6.12/revert-drm-xe-gt-update-handling-of-xe_force_wake_get-return.patch new file mode 100644 index 0000000000..be9dc4e5c1 --- /dev/null +++ b/queue-6.12/revert-drm-xe-gt-update-handling-of-xe_force_wake_get-return.patch @@ -0,0 +1,334 @@ +From stable+bounces-165052-greg=kroah.com@vger.kernel.org Tue Jul 29 13:05:48 2025 +From: Tomita Moeko +Date: Tue, 29 Jul 2025 19:05:22 +0800 +Subject: Revert "drm/xe/gt: Update handling of xe_force_wake_get return" +To: "Lucas De Marchi" , "Thomas Hellström" , "Rodrigo Vivi" +Cc: intel-xe@lists.freedesktop.org, stable@vger.kernel.org, Tomita Moeko , Badal Nilawar , Matthew Brost , Himal Prasad Ghimiray , Nirmoy Das +Message-ID: <20250729110525.49838-2-tomitamoeko@gmail.com> + +From: Tomita Moeko + +This reverts commit d42b44736ea29fa6d0c3cb9c75569314134b7732. + +The reverted commit updated the handling of xe_force_wake_get to match +the new "return refcounted domain mask" semantics introduced in commit +a7ddcea1f5ac ("drm/xe: Error handling in xe_force_wake_get()"). However, +that API change only exists in 6.13 and later. + +In 6.12 stable kernel, xe_force_wake_get still returns a status code. +The update incorrectly treats the return value as a mask, causing the +return value of 0 to be misinterpreted as an error. As a result, the +driver probe fails with -ETIMEDOUT in xe_pci_probe -> xe_device_probe +-> xe_gt_init_hwconfig -> xe_force_wake_get. + +[ 1254.323172] xe 0000:00:02.0: [drm] Found ALDERLAKE_P (device ID 46a6) display version 13.00 stepping D0 +[ 1254.323175] xe 0000:00:02.0: [drm:xe_pci_probe [xe]] ALDERLAKE_P 46a6:000c dgfx:0 gfx:Xe_LP (12.00) media:Xe_M (12.00) display:yes dma_m_s:39 tc:1 gscfi:0 cscfi:0 +[ 1254.323275] xe 0000:00:02.0: [drm:xe_pci_probe [xe]] Stepping = (G:C0, M:C0, B:**) +[ 1254.323328] xe 0000:00:02.0: [drm:xe_pci_probe [xe]] SR-IOV support: no (mode: none) +[ 1254.323379] xe 0000:00:02.0: [drm:intel_pch_type [xe]] Found Alder Lake PCH +[ 1254.323475] xe 0000:00:02.0: probe with driver xe failed with error -110 + +Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/5373 +Cc: Badal Nilawar +Cc: Matthew Brost +Cc: Rodrigo Vivi +Cc: Lucas De Marchi +Cc: Himal Prasad Ghimiray +Cc: Nirmoy Das +Acked-by: Rodrigo Vivi +Signed-off-by: Tomita Moeko +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/xe/xe_gt.c | 105 ++++++++++++++++++++------------------------- + 1 file changed, 47 insertions(+), 58 deletions(-) + +--- a/drivers/gpu/drm/xe/xe_gt.c ++++ b/drivers/gpu/drm/xe/xe_gt.c +@@ -98,14 +98,14 @@ void xe_gt_sanitize(struct xe_gt *gt) + + static void xe_gt_enable_host_l2_vram(struct xe_gt *gt) + { +- unsigned int fw_ref; + u32 reg; ++ int err; + + if (!XE_WA(gt, 16023588340)) + return; + +- fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); +- if (!fw_ref) ++ err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); ++ if (WARN_ON(err)) + return; + + if (!xe_gt_is_media_type(gt)) { +@@ -115,13 +115,13 @@ static void xe_gt_enable_host_l2_vram(st + } + + xe_gt_mcr_multicast_write(gt, XEHPC_L3CLOS_MASK(3), 0xF); +- xe_force_wake_put(gt_to_fw(gt), fw_ref); ++ xe_force_wake_put(gt_to_fw(gt), XE_FW_GT); + } + + static void xe_gt_disable_host_l2_vram(struct xe_gt *gt) + { +- unsigned int fw_ref; + u32 reg; ++ int err; + + if (!XE_WA(gt, 16023588340)) + return; +@@ -129,15 +129,15 @@ static void xe_gt_disable_host_l2_vram(s + if (xe_gt_is_media_type(gt)) + return; + +- fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); +- if (!fw_ref) ++ err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); ++ if (WARN_ON(err)) + return; + + reg = xe_gt_mcr_unicast_read_any(gt, XE2_GAMREQSTRM_CTRL); + reg &= ~CG_DIS_CNTLBUS; + xe_gt_mcr_multicast_write(gt, XE2_GAMREQSTRM_CTRL, reg); + +- xe_force_wake_put(gt_to_fw(gt), fw_ref); ++ xe_force_wake_put(gt_to_fw(gt), XE_FW_GT); + } + + /** +@@ -407,14 +407,11 @@ static void dump_pat_on_error(struct xe_ + + static int gt_fw_domain_init(struct xe_gt *gt) + { +- unsigned int fw_ref; + int err, i; + +- fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); +- if (!fw_ref) { +- err = -ETIMEDOUT; ++ err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); ++ if (err) + goto err_hw_fence_irq; +- } + + if (!xe_gt_is_media_type(gt)) { + err = xe_ggtt_init(gt_to_tile(gt)->mem.ggtt); +@@ -449,12 +446,14 @@ static int gt_fw_domain_init(struct xe_g + */ + gt->info.gmdid = xe_mmio_read32(gt, GMD_ID); + +- xe_force_wake_put(gt_to_fw(gt), fw_ref); ++ err = xe_force_wake_put(gt_to_fw(gt), XE_FW_GT); ++ XE_WARN_ON(err); ++ + return 0; + + err_force_wake: + dump_pat_on_error(gt); +- xe_force_wake_put(gt_to_fw(gt), fw_ref); ++ xe_force_wake_put(gt_to_fw(gt), XE_FW_GT); + err_hw_fence_irq: + for (i = 0; i < XE_ENGINE_CLASS_MAX; ++i) + xe_hw_fence_irq_finish(>->fence_irq[i]); +@@ -464,14 +463,11 @@ err_hw_fence_irq: + + static int all_fw_domain_init(struct xe_gt *gt) + { +- unsigned int fw_ref; + int err, i; + +- fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); +- if (!xe_force_wake_ref_has_domain(fw_ref, XE_FORCEWAKE_ALL)) { +- err = -ETIMEDOUT; +- goto err_force_wake; +- } ++ err = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); ++ if (err) ++ goto err_hw_fence_irq; + + xe_gt_mcr_set_implicit_defaults(gt); + xe_wa_process_gt(gt); +@@ -537,12 +533,14 @@ static int all_fw_domain_init(struct xe_ + if (IS_SRIOV_PF(gt_to_xe(gt))) + xe_gt_sriov_pf_init_hw(gt); + +- xe_force_wake_put(gt_to_fw(gt), fw_ref); ++ err = xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL); ++ XE_WARN_ON(err); + + return 0; + + err_force_wake: +- xe_force_wake_put(gt_to_fw(gt), fw_ref); ++ xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL); ++err_hw_fence_irq: + for (i = 0; i < XE_ENGINE_CLASS_MAX; ++i) + xe_hw_fence_irq_finish(>->fence_irq[i]); + +@@ -555,12 +553,11 @@ err_force_wake: + */ + int xe_gt_init_hwconfig(struct xe_gt *gt) + { +- unsigned int fw_ref; + int err; + +- fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); +- if (!fw_ref) +- return -ETIMEDOUT; ++ err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); ++ if (err) ++ goto out; + + xe_gt_mcr_init_early(gt); + xe_pat_init(gt); +@@ -578,7 +575,8 @@ int xe_gt_init_hwconfig(struct xe_gt *gt + xe_gt_enable_host_l2_vram(gt); + + out_fw: +- xe_force_wake_put(gt_to_fw(gt), fw_ref); ++ xe_force_wake_put(gt_to_fw(gt), XE_FW_GT); ++out: + return err; + } + +@@ -746,7 +744,6 @@ static int do_gt_restart(struct xe_gt *g + + static int gt_reset(struct xe_gt *gt) + { +- unsigned int fw_ref; + int err; + + if (xe_device_wedged(gt_to_xe(gt))) +@@ -767,11 +764,9 @@ static int gt_reset(struct xe_gt *gt) + + xe_gt_sanitize(gt); + +- fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); +- if (!xe_force_wake_ref_has_domain(fw_ref, XE_FORCEWAKE_ALL)) { +- err = -ETIMEDOUT; +- goto err_out; +- } ++ err = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); ++ if (err) ++ goto err_msg; + + if (IS_SRIOV_PF(gt_to_xe(gt))) + xe_gt_sriov_pf_stop_prepare(gt); +@@ -792,7 +787,8 @@ static int gt_reset(struct xe_gt *gt) + if (err) + goto err_out; + +- xe_force_wake_put(gt_to_fw(gt), fw_ref); ++ err = xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL); ++ XE_WARN_ON(err); + xe_pm_runtime_put(gt_to_xe(gt)); + + xe_gt_info(gt, "reset done\n"); +@@ -800,7 +796,8 @@ static int gt_reset(struct xe_gt *gt) + return 0; + + err_out: +- xe_force_wake_put(gt_to_fw(gt), fw_ref); ++ XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL)); ++err_msg: + XE_WARN_ON(xe_uc_start(>->uc)); + err_fail: + xe_gt_err(gt, "reset failed (%pe)\n", ERR_PTR(err)); +@@ -832,25 +829,22 @@ void xe_gt_reset_async(struct xe_gt *gt) + + void xe_gt_suspend_prepare(struct xe_gt *gt) + { +- unsigned int fw_ref; +- +- fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); ++ XE_WARN_ON(xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL)); + + xe_uc_suspend_prepare(>->uc); + +- xe_force_wake_put(gt_to_fw(gt), fw_ref); ++ XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL)); + } + + int xe_gt_suspend(struct xe_gt *gt) + { +- unsigned int fw_ref; + int err; + + xe_gt_dbg(gt, "suspending\n"); + xe_gt_sanitize(gt); + +- fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); +- if (!xe_force_wake_ref_has_domain(fw_ref, XE_FORCEWAKE_ALL)) ++ err = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); ++ if (err) + goto err_msg; + + err = xe_uc_suspend(>->uc); +@@ -861,15 +855,14 @@ int xe_gt_suspend(struct xe_gt *gt) + + xe_gt_disable_host_l2_vram(gt); + +- xe_force_wake_put(gt_to_fw(gt), fw_ref); ++ XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL)); + xe_gt_dbg(gt, "suspended\n"); + + return 0; + +-err_msg: +- err = -ETIMEDOUT; + err_force_wake: +- xe_force_wake_put(gt_to_fw(gt), fw_ref); ++ XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL)); ++err_msg: + xe_gt_err(gt, "suspend failed (%pe)\n", ERR_PTR(err)); + + return err; +@@ -877,11 +870,9 @@ err_force_wake: + + void xe_gt_shutdown(struct xe_gt *gt) + { +- unsigned int fw_ref; +- +- fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); ++ xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); + do_gt_reset(gt); +- xe_force_wake_put(gt_to_fw(gt), fw_ref); ++ xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL); + } + + /** +@@ -906,12 +897,11 @@ int xe_gt_sanitize_freq(struct xe_gt *gt + + int xe_gt_resume(struct xe_gt *gt) + { +- unsigned int fw_ref; + int err; + + xe_gt_dbg(gt, "resuming\n"); +- fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); +- if (!xe_force_wake_ref_has_domain(fw_ref, XE_FORCEWAKE_ALL)) ++ err = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); ++ if (err) + goto err_msg; + + err = do_gt_restart(gt); +@@ -920,15 +910,14 @@ int xe_gt_resume(struct xe_gt *gt) + + xe_gt_idle_enable_pg(gt); + +- xe_force_wake_put(gt_to_fw(gt), fw_ref); ++ XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL)); + xe_gt_dbg(gt, "resumed\n"); + + return 0; + +-err_msg: +- err = -ETIMEDOUT; + err_force_wake: +- xe_force_wake_put(gt_to_fw(gt), fw_ref); ++ XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL)); ++err_msg: + xe_gt_err(gt, "resume failed (%pe)\n", ERR_PTR(err)); + + return err; diff --git a/queue-6.12/revert-drm-xe-tests-mocs-update-xe_force_wake_get-return-handling.patch b/queue-6.12/revert-drm-xe-tests-mocs-update-xe_force_wake_get-return-handling.patch new file mode 100644 index 0000000000..baef0490d8 --- /dev/null +++ b/queue-6.12/revert-drm-xe-tests-mocs-update-xe_force_wake_get-return-handling.patch @@ -0,0 +1,91 @@ +From stable+bounces-165053-greg=kroah.com@vger.kernel.org Tue Jul 29 13:05:55 2025 +From: Tomita Moeko +Date: Tue, 29 Jul 2025 19:05:23 +0800 +Subject: Revert "drm/xe/tests/mocs: Update xe_force_wake_get() return handling" +To: "Lucas De Marchi" , "Thomas Hellström" , "Rodrigo Vivi" +Cc: intel-xe@lists.freedesktop.org, stable@vger.kernel.org, Tomita Moeko , Himal Prasad Ghimiray , Nirmoy Das , Badal Nilawar +Message-ID: <20250729110525.49838-3-tomitamoeko@gmail.com> + +From: Tomita Moeko + +This reverts commit 95a75ed2b005447f96fbd4ac61758ccda44069d1. + +The reverted commit updated the handling of xe_force_wake_get to match +the new "return refcounted domain mask" semantics introduced in commit +a7ddcea1f5ac ("drm/xe: Error handling in xe_force_wake_get()"). However, +that API change only exists in 6.13 and later. + +In 6.12 stable kernel, xe_force_wake_get still returns a status code. +The update incorrectly treats the return value as a mask, causing the +return value of 0 to be misinterpreted as an error. + +Cc: Rodrigo Vivi +Cc: Lucas De Marchi +Cc: Himal Prasad Ghimiray +Cc: Nirmoy Das +Cc: Badal Nilawar +Acked-by: Rodrigo Vivi +Signed-off-by: Tomita Moeko +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/xe/tests/xe_mocs.c | 21 ++++++++++----------- + 1 file changed, 10 insertions(+), 11 deletions(-) + +--- a/drivers/gpu/drm/xe/tests/xe_mocs.c ++++ b/drivers/gpu/drm/xe/tests/xe_mocs.c +@@ -43,14 +43,12 @@ static void read_l3cc_table(struct xe_gt + { + struct kunit *test = kunit_get_current_test(); + u32 l3cc, l3cc_expected; +- unsigned int fw_ref, i; ++ unsigned int i; + u32 reg_val; ++ u32 ret; + +- fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); +- if (!xe_force_wake_ref_has_domain(fw_ref, XE_FORCEWAKE_ALL)) { +- xe_force_wake_put(gt_to_fw(gt), fw_ref); +- KUNIT_ASSERT_TRUE_MSG(test, true, "Forcewake Failed.\n"); +- } ++ ret = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); ++ KUNIT_ASSERT_EQ_MSG(test, ret, 0, "Forcewake Failed.\n"); + + for (i = 0; i < info->num_mocs_regs; i++) { + if (!(i & 1)) { +@@ -74,7 +72,7 @@ static void read_l3cc_table(struct xe_gt + KUNIT_EXPECT_EQ_MSG(test, l3cc_expected, l3cc, + "l3cc idx=%u has incorrect val.\n", i); + } +- xe_force_wake_put(gt_to_fw(gt), fw_ref); ++ xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL); + } + + static void read_mocs_table(struct xe_gt *gt, +@@ -82,14 +80,15 @@ static void read_mocs_table(struct xe_gt + { + struct kunit *test = kunit_get_current_test(); + u32 mocs, mocs_expected; +- unsigned int fw_ref, i; ++ unsigned int i; + u32 reg_val; ++ u32 ret; + + KUNIT_EXPECT_TRUE_MSG(test, info->unused_entries_index, + "Unused entries index should have been defined\n"); + +- fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); +- KUNIT_ASSERT_NE_MSG(test, fw_ref, 0, "Forcewake Failed.\n"); ++ ret = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); ++ KUNIT_ASSERT_EQ_MSG(test, ret, 0, "Forcewake Failed.\n"); + + for (i = 0; i < info->num_mocs_regs; i++) { + if (regs_are_mcr(gt)) +@@ -107,7 +106,7 @@ static void read_mocs_table(struct xe_gt + "mocs reg 0x%x has incorrect val.\n", i); + } + +- xe_force_wake_put(gt_to_fw(gt), fw_ref); ++ xe_force_wake_put(gt_to_fw(gt), XE_FW_GT); + } + + static int mocs_kernel_test_run_device(struct xe_device *xe) diff --git a/queue-6.12/series b/queue-6.12/series index fd9902d862..a16a82dcb7 100644 --- a/queue-6.12/series +++ b/queue-6.12/series @@ -106,3 +106,10 @@ iio-hid-sensor-prox-restore-lost-scale-assignments.patch iio-hid-sensor-prox-fix-incorrect-offset-calculation.patch arm-9448-1-use-an-absolute-path-to-unified.h-in-kbuild_aflags.patch drivers-hv-make-the-sysfs-node-size-for-the-ring-buffer-dynamic.patch +alsa-hda-tegra-add-tegra264-support.patch +alsa-hda-add-missing-nvidia-hda-codec-ids.patch +drm-i915-dp-fix-2.7-gbps-dp_link_bw-value-on-g4x.patch +revert-drm-xe-gt-update-handling-of-xe_force_wake_get-return.patch +revert-drm-xe-tests-mocs-update-xe_force_wake_get-return-handling.patch +revert-drm-xe-devcoredump-update-handling-of-xe_force_wake_get-return.patch +revert-drm-xe-forcewake-add-a-helper-xe_force_wake_ref_has_domain.patch