From: Sasha Levin Date: Mon, 12 Sep 2022 10:56:16 +0000 (-0400) Subject: Fixes for 5.15 X-Git-Tag: v5.19.9~26 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=9380a908da55c6876a5b3638e80c7d0a07d3eafc;p=thirdparty%2Fkernel%2Fstable-queue.git Fixes for 5.15 Signed-off-by: Sasha Levin --- diff --git a/queue-5.15/hwmon-mr75203-enable-polling-for-all-vm-channels.patch b/queue-5.15/hwmon-mr75203-enable-polling-for-all-vm-channels.patch new file mode 100644 index 00000000000..3fcf10313ef --- /dev/null +++ b/queue-5.15/hwmon-mr75203-enable-polling-for-all-vm-channels.patch @@ -0,0 +1,51 @@ +From def77c93b995f48bd30342be298ebc9ea491d187 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 8 Sep 2022 15:24:34 +0000 +Subject: hwmon: (mr75203) enable polling for all VM channels + +From: Eliav Farber + +[ Upstream commit e43212e0f55dc2d6b15d6c174cc0a64b25fab5e7 ] + +Configure ip-polling register to enable polling for all voltage monitor +channels. +This enables reading the voltage values for all inputs other than just +input 0. + +Fixes: 9d823351a337 ("hwmon: Add hardware monitoring driver for Moortec MR75203 PVT controller") +Signed-off-by: Eliav Farber +Reviewed-by: Andy Shevchenko +Link: https://lore.kernel.org/r/20220908152449.35457-7-farbere@amazon.com +Signed-off-by: Guenter Roeck +Signed-off-by: Sasha Levin +--- + drivers/hwmon/mr75203.c | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +diff --git a/drivers/hwmon/mr75203.c b/drivers/hwmon/mr75203.c +index e62fae1491c85..05da83841536f 100644 +--- a/drivers/hwmon/mr75203.c ++++ b/drivers/hwmon/mr75203.c +@@ -398,6 +398,19 @@ static int pvt_init(struct pvt_device *pvt) + if (ret) + return ret; + ++ val = (BIT(pvt->c_num) - 1) | VM_CH_INIT | ++ IP_POLL << SDIF_ADDR_SFT | SDIF_WRN_W | SDIF_PROG; ++ ret = regmap_write(v_map, SDIF_W, val); ++ if (ret < 0) ++ return ret; ++ ++ ret = regmap_read_poll_timeout(v_map, SDIF_STAT, ++ val, !(val & SDIF_BUSY), ++ PVT_POLL_DELAY_US, ++ PVT_POLL_TIMEOUT_US); ++ if (ret) ++ return ret; ++ + val = CFG1_VOL_MEAS_MODE | CFG1_PARALLEL_OUT | + CFG1_14_BIT | IP_CFG << SDIF_ADDR_SFT | + SDIF_WRN_W | SDIF_PROG; +-- +2.35.1 + diff --git a/queue-5.15/hwmon-mr75203-fix-multi-channel-voltage-reading.patch b/queue-5.15/hwmon-mr75203-fix-multi-channel-voltage-reading.patch new file mode 100644 index 00000000000..b99ee4d5206 --- /dev/null +++ b/queue-5.15/hwmon-mr75203-fix-multi-channel-voltage-reading.patch @@ -0,0 +1,136 @@ +From afd4980d34f788f4638eb50c959f99ab5226abda Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 8 Sep 2022 15:24:33 +0000 +Subject: hwmon: (mr75203) fix multi-channel voltage reading + +From: Eliav Farber + +[ Upstream commit 91a9e063cdcfca8fe642b078d6fae4ce49187975 ] + +Fix voltage allocation and reading to support all channels in all VMs. +Prior to this change allocation and reading were done only for the first +channel in each VM. +This change counts the total number of channels for allocation, and takes +into account the channel offset when reading the sample data register. + +Fixes: 9d823351a337 ("hwmon: Add hardware monitoring driver for Moortec MR75203 PVT controller") +Signed-off-by: Eliav Farber +Reviewed-by: Andy Shevchenko +Link: https://lore.kernel.org/r/20220908152449.35457-6-farbere@amazon.com +Signed-off-by: Guenter Roeck +Signed-off-by: Sasha Levin +--- + drivers/hwmon/mr75203.c | 29 +++++++++++++++++------------ + 1 file changed, 17 insertions(+), 12 deletions(-) + +diff --git a/drivers/hwmon/mr75203.c b/drivers/hwmon/mr75203.c +index 630d596d4317f..e62fae1491c85 100644 +--- a/drivers/hwmon/mr75203.c ++++ b/drivers/hwmon/mr75203.c +@@ -68,8 +68,9 @@ + + /* VM Individual Macro Register */ + #define VM_COM_REG_SIZE 0x200 +-#define VM_SDIF_DONE(n) (VM_COM_REG_SIZE + 0x34 + 0x200 * (n)) +-#define VM_SDIF_DATA(n) (VM_COM_REG_SIZE + 0x40 + 0x200 * (n)) ++#define VM_SDIF_DONE(vm) (VM_COM_REG_SIZE + 0x34 + 0x200 * (vm)) ++#define VM_SDIF_DATA(vm, ch) \ ++ (VM_COM_REG_SIZE + 0x40 + 0x200 * (vm) + 0x4 * (ch)) + + /* SDA Slave Register */ + #define IP_CTRL 0x00 +@@ -115,6 +116,7 @@ struct pvt_device { + u32 t_num; + u32 p_num; + u32 v_num; ++ u32 c_num; + u32 ip_freq; + u8 *vm_idx; + }; +@@ -178,14 +180,15 @@ static int pvt_read_in(struct device *dev, u32 attr, int channel, long *val) + { + struct pvt_device *pvt = dev_get_drvdata(dev); + struct regmap *v_map = pvt->v_map; ++ u8 vm_idx, ch_idx; + u32 n, stat; +- u8 vm_idx; + int ret; + +- if (channel >= pvt->v_num) ++ if (channel >= pvt->v_num * pvt->c_num) + return -EINVAL; + +- vm_idx = pvt->vm_idx[channel]; ++ vm_idx = pvt->vm_idx[channel / pvt->c_num]; ++ ch_idx = channel % pvt->c_num; + + switch (attr) { + case hwmon_in_input: +@@ -196,7 +199,7 @@ static int pvt_read_in(struct device *dev, u32 attr, int channel, long *val) + if (ret) + return ret; + +- ret = regmap_read(v_map, VM_SDIF_DATA(vm_idx), &n); ++ ret = regmap_read(v_map, VM_SDIF_DATA(vm_idx, ch_idx), &n); + if(ret < 0) + return ret; + +@@ -509,8 +512,8 @@ static int pvt_reset_control_deassert(struct device *dev, struct pvt_device *pvt + + static int mr75203_probe(struct platform_device *pdev) + { ++ u32 ts_num, vm_num, pd_num, ch_num, val, index, i; + const struct hwmon_channel_info **pvt_info; +- u32 ts_num, vm_num, pd_num, val, index, i; + struct device *dev = &pdev->dev; + u32 *temp_config, *in_config; + struct device *hwmon_dev; +@@ -551,9 +554,11 @@ static int mr75203_probe(struct platform_device *pdev) + ts_num = (val & TS_NUM_MSK) >> TS_NUM_SFT; + pd_num = (val & PD_NUM_MSK) >> PD_NUM_SFT; + vm_num = (val & VM_NUM_MSK) >> VM_NUM_SFT; ++ ch_num = (val & CH_NUM_MSK) >> CH_NUM_SFT; + pvt->t_num = ts_num; + pvt->p_num = pd_num; + pvt->v_num = vm_num; ++ pvt->c_num = ch_num; + val = 0; + if (ts_num) + val++; +@@ -590,7 +595,7 @@ static int mr75203_probe(struct platform_device *pdev) + } + + if (vm_num) { +- u32 num = vm_num; ++ u32 total_ch; + + ret = pvt_get_regmap(pdev, "vm", pvt); + if (ret) +@@ -614,20 +619,20 @@ static int mr75203_probe(struct platform_device *pdev) + for (i = 0; i < vm_num; i++) + if (pvt->vm_idx[i] >= vm_num || + pvt->vm_idx[i] == 0xff) { +- num = i; + pvt->v_num = i; + vm_num = i; + break; + } + } + +- in_config = devm_kcalloc(dev, num + 1, ++ total_ch = ch_num * vm_num; ++ in_config = devm_kcalloc(dev, total_ch + 1, + sizeof(*in_config), GFP_KERNEL); + if (!in_config) + return -ENOMEM; + +- memset32(in_config, HWMON_I_INPUT, num); +- in_config[num] = 0; ++ memset32(in_config, HWMON_I_INPUT, total_ch); ++ in_config[total_ch] = 0; + pvt_in.config = in_config; + + pvt_info[index++] = &pvt_in; +-- +2.35.1 + diff --git a/queue-5.15/hwmon-mr75203-fix-vm-sensor-allocation-when-intel-vm.patch b/queue-5.15/hwmon-mr75203-fix-vm-sensor-allocation-when-intel-vm.patch new file mode 100644 index 00000000000..8c9656db535 --- /dev/null +++ b/queue-5.15/hwmon-mr75203-fix-vm-sensor-allocation-when-intel-vm.patch @@ -0,0 +1,71 @@ +From d0f7528b65c3114fbe05c586351149038a0c1ba7 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 8 Sep 2022 15:24:30 +0000 +Subject: hwmon: (mr75203) fix VM sensor allocation when "intel,vm-map" not + defined + +From: Eliav Farber + +[ Upstream commit 81114fc3d27bf5b06b2137d2fd2b63da656a8b90 ] + +Bug - in case "intel,vm-map" is missing in device-tree ,'num' is set +to 0, and no voltage channel infos are allocated. + +The reason num is set to 0 when "intel,vm-map" is missing is to set the +entire pvt->vm_idx[] with incremental channel numbers, but it didn't +take into consideration that same num is used later in devm_kcalloc(). + +If "intel,vm-map" does exist there is no need to set the unspecified +channels with incremental numbers, because the unspecified channels +can't be accessed in pvt_read_in() which is the only other place besides +the probe functions that uses pvt->vm_idx[]. + +This change fixes the bug by moving the incremental channel numbers +setting to be done only if "intel,vm-map" property is defined (starting +loop from 0), and removing 'num = 0'. + +Fixes: 9d823351a337 ("hwmon: Add hardware monitoring driver for Moortec MR75203 PVT controller") +Signed-off-by: Eliav Farber +Reviewed-by: Andy Shevchenko +Link: https://lore.kernel.org/r/20220908152449.35457-3-farbere@amazon.com +Signed-off-by: Guenter Roeck +Signed-off-by: Sasha Levin +--- + drivers/hwmon/mr75203.c | 14 ++++++-------- + 1 file changed, 6 insertions(+), 8 deletions(-) + +diff --git a/drivers/hwmon/mr75203.c b/drivers/hwmon/mr75203.c +index 1ba1e31459690..36cbc86033ce9 100644 +--- a/drivers/hwmon/mr75203.c ++++ b/drivers/hwmon/mr75203.c +@@ -594,7 +594,12 @@ static int mr75203_probe(struct platform_device *pdev) + ret = device_property_read_u8_array(dev, "intel,vm-map", + pvt->vm_idx, vm_num); + if (ret) { +- num = 0; ++ /* ++ * Incase intel,vm-map property is not defined, we ++ * assume incremental channel numbers. ++ */ ++ for (i = 0; i < vm_num; i++) ++ pvt->vm_idx[i] = i; + } else { + for (i = 0; i < vm_num; i++) + if (pvt->vm_idx[i] >= vm_num || +@@ -604,13 +609,6 @@ static int mr75203_probe(struct platform_device *pdev) + } + } + +- /* +- * Incase intel,vm-map property is not defined, we assume +- * incremental channel numbers. +- */ +- for (i = num; i < vm_num; i++) +- pvt->vm_idx[i] = i; +- + in_config = devm_kcalloc(dev, num + 1, + sizeof(*in_config), GFP_KERNEL); + if (!in_config) +-- +2.35.1 + diff --git a/queue-5.15/hwmon-mr75203-fix-voltage-equation-for-negative-sour.patch b/queue-5.15/hwmon-mr75203-fix-voltage-equation-for-negative-sour.patch new file mode 100644 index 00000000000..afafa11e8de --- /dev/null +++ b/queue-5.15/hwmon-mr75203-fix-voltage-equation-for-negative-sour.patch @@ -0,0 +1,70 @@ +From 77002a855373b66a1d26ce1c606514828510e67d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 8 Sep 2022 15:24:32 +0000 +Subject: hwmon: (mr75203) fix voltage equation for negative source input + +From: Eliav Farber + +[ Upstream commit 227a3a2fc31d8e4bb9c88d4804e19530af245b1b ] + +According to Moortec Embedded Voltage Monitor (MEVM) series 3 data +sheet, the minimum input signal is -100mv and maximum input signal +is +1000mv. + +The equation used to convert the digital word to voltage uses mixed +types (*val signed and n unsigned), and on 64 bit machines also has +different size, since sizeof(u32) = 4 and sizeof(long) = 8. + +So when measuring a negative input, n will be small enough, such that +PVT_N_CONST * n < PVT_R_CONST, and the result of +(PVT_N_CONST * n - PVT_R_CONST) will overflow to a very big positive +32 bit number. Then when storing the result in *val it will be the same +value just in 64 bit (instead of it representing a negative number which +will what happen when sizeof(long) = 4). + +When -1023 <= (PVT_N_CONST * n - PVT_R_CONST) <= -1 +dividing the number by 1024 should result of in 0, but because ">> 10" +is used, and the sign bit is used to fill the vacated bit positions, it +results in -1 (0xf...fffff) which is wrong. + +This change fixes the sign problem and supports negative values by +casting n to long and replacing the shift right with div operation. + +Fixes: 9d823351a337 ("hwmon: Add hardware monitoring driver for Moortec MR75203 PVT controller") +Signed-off-by: Eliav Farber +Reviewed-by: Andy Shevchenko +Link: https://lore.kernel.org/r/20220908152449.35457-5-farbere@amazon.com +Signed-off-by: Guenter Roeck +Signed-off-by: Sasha Levin +--- + drivers/hwmon/mr75203.c | 14 ++++++++++++-- + 1 file changed, 12 insertions(+), 2 deletions(-) + +diff --git a/drivers/hwmon/mr75203.c b/drivers/hwmon/mr75203.c +index 6e6aa61ea632b..630d596d4317f 100644 +--- a/drivers/hwmon/mr75203.c ++++ b/drivers/hwmon/mr75203.c +@@ -201,8 +201,18 @@ static int pvt_read_in(struct device *dev, u32 attr, int channel, long *val) + return ret; + + n &= SAMPLE_DATA_MSK; +- /* Convert the N bitstream count into voltage */ +- *val = (PVT_N_CONST * n - PVT_R_CONST) >> PVT_CONV_BITS; ++ /* ++ * Convert the N bitstream count into voltage. ++ * To support negative voltage calculation for 64bit machines ++ * n must be cast to long, since n and *val differ both in ++ * signedness and in size. ++ * Division is used instead of right shift, because for signed ++ * numbers, the sign bit is used to fill the vacated bit ++ * positions, and if the number is negative, 1 is used. ++ * BIT(x) may not be used instead of (1 << x) because it's ++ * unsigned. ++ */ ++ *val = (PVT_N_CONST * (long)n - PVT_R_CONST) / (1 << PVT_CONV_BITS); + + return 0; + default: +-- +2.35.1 + diff --git a/queue-5.15/hwmon-mr75203-update-pvt-v_num-and-vm_num-to-the-act.patch b/queue-5.15/hwmon-mr75203-update-pvt-v_num-and-vm_num-to-the-act.patch new file mode 100644 index 00000000000..76bfd7f5a98 --- /dev/null +++ b/queue-5.15/hwmon-mr75203-update-pvt-v_num-and-vm_num-to-the-act.patch @@ -0,0 +1,42 @@ +From e911300bc3b8bb7d0403d9e00b8d0d03c1c457d7 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 8 Sep 2022 15:24:31 +0000 +Subject: hwmon: (mr75203) update pvt->v_num and vm_num to the actual number of + used sensors + +From: Eliav Farber + +[ Upstream commit bb9195bd6664d94d71647631593e09f705ff5edd ] + +This issue is relevant when "intel,vm-map" is set in device-tree, and +defines a lower number of VMs than actually supported. + +This change is needed for all places that use pvt->v_num or vm_num +later on in the code. + +Fixes: 9d823351a337 ("hwmon: Add hardware monitoring driver for Moortec MR75203 PVT controller") +Signed-off-by: Eliav Farber +Reviewed-by: Andy Shevchenko +Link: https://lore.kernel.org/r/20220908152449.35457-4-farbere@amazon.com +Signed-off-by: Guenter Roeck +Signed-off-by: Sasha Levin +--- + drivers/hwmon/mr75203.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/hwmon/mr75203.c b/drivers/hwmon/mr75203.c +index 36cbc86033ce9..6e6aa61ea632b 100644 +--- a/drivers/hwmon/mr75203.c ++++ b/drivers/hwmon/mr75203.c +@@ -605,6 +605,8 @@ static int mr75203_probe(struct platform_device *pdev) + if (pvt->vm_idx[i] >= vm_num || + pvt->vm_idx[i] == 0xff) { + num = i; ++ pvt->v_num = i; ++ vm_num = i; + break; + } + } +-- +2.35.1 + diff --git a/queue-5.15/i40e-fix-adq-rate-limiting-for-pf.patch b/queue-5.15/i40e-fix-adq-rate-limiting-for-pf.patch new file mode 100644 index 00000000000..f8804d69a7b --- /dev/null +++ b/queue-5.15/i40e-fix-adq-rate-limiting-for-pf.patch @@ -0,0 +1,58 @@ +From bc1ecd8de8558fdc63aa530016d61ecb23ea2c7b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 9 Aug 2022 10:57:44 +0200 +Subject: i40e: Fix ADQ rate limiting for PF + +From: Przemyslaw Patynowski + +[ Upstream commit 45bb006d3c924b1201ed43c87a96b437662dcaa8 ] + +Fix HW rate limiting for ADQ. +Fallback to kernel queue selection for ADQ, as it is network stack +that decides which queue to use for transmit with ADQ configured. +Reset PF after creation of VMDq2 VSIs required for ADQ, as to +reprogram TX queue contexts in i40e_configure_tx_ring. +Without this patch PF would limit TX rate only according to TC0. + +Fixes: a9ce82f744dc ("i40e: Enable 'channel' mode in mqprio for TC configs") +Signed-off-by: Przemyslaw Patynowski +Signed-off-by: Jan Sokolowski +Tested-by: Bharathi Sreenivas +Signed-off-by: Tony Nguyen +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/intel/i40e/i40e_main.c | 3 +++ + drivers/net/ethernet/intel/i40e/i40e_txrx.c | 3 ++- + 2 files changed, 5 insertions(+), 1 deletion(-) + +diff --git a/drivers/net/ethernet/intel/i40e/i40e_main.c b/drivers/net/ethernet/intel/i40e/i40e_main.c +index f373072dd3b30..ce6eea7a60027 100644 +--- a/drivers/net/ethernet/intel/i40e/i40e_main.c ++++ b/drivers/net/ethernet/intel/i40e/i40e_main.c +@@ -6517,6 +6517,9 @@ static int i40e_configure_queue_channels(struct i40e_vsi *vsi) + vsi->tc_seid_map[i] = ch->seid; + } + } ++ ++ /* reset to reconfigure TX queue contexts */ ++ i40e_do_reset(vsi->back, I40E_PF_RESET_FLAG, true); + return ret; + + err_free: +diff --git a/drivers/net/ethernet/intel/i40e/i40e_txrx.c b/drivers/net/ethernet/intel/i40e/i40e_txrx.c +index d3a4a33977ee8..326fd25d055f8 100644 +--- a/drivers/net/ethernet/intel/i40e/i40e_txrx.c ++++ b/drivers/net/ethernet/intel/i40e/i40e_txrx.c +@@ -3651,7 +3651,8 @@ u16 i40e_lan_select_queue(struct net_device *netdev, + u8 prio; + + /* is DCB enabled at all? */ +- if (vsi->tc_config.numtc == 1) ++ if (vsi->tc_config.numtc == 1 || ++ i40e_is_tc_mqprio_enabled(vsi->back)) + return netdev_pick_tx(netdev, skb, sb_dev); + + prio = skb->priority; +-- +2.35.1 + diff --git a/queue-5.15/i40e-refactor-tc-mqprio-checks.patch b/queue-5.15/i40e-refactor-tc-mqprio-checks.patch new file mode 100644 index 00000000000..4e63fd3d1c0 --- /dev/null +++ b/queue-5.15/i40e-refactor-tc-mqprio-checks.patch @@ -0,0 +1,157 @@ +From 36c35b2ca2345ecc7e14660f19e4b043d4b195d2 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 8 Jun 2022 13:52:48 +0200 +Subject: i40e: Refactor tc mqprio checks + +From: Przemyslaw Patynowski + +[ Upstream commit 2313e69c84c024a85d017a60ae925085de47530a ] + +Refactor bitwise checks for whether TC MQPRIO is enabled +into one single method for improved readability. + +Signed-off-by: Przemyslaw Patynowski +Signed-off-by: Jan Sokolowski +Tested-by: Bharathi Sreenivas +Signed-off-by: Tony Nguyen +Stable-dep-of: 45bb006d3c92 ("i40e: Fix ADQ rate limiting for PF") +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/intel/i40e/i40e.h | 14 +++++++++++++ + .../net/ethernet/intel/i40e/i40e_ethtool.c | 2 +- + drivers/net/ethernet/intel/i40e/i40e_main.c | 20 +++++++++---------- + 3 files changed, 25 insertions(+), 11 deletions(-) + +diff --git a/drivers/net/ethernet/intel/i40e/i40e.h b/drivers/net/ethernet/intel/i40e/i40e.h +index 210f09118edea..0f19c237cb587 100644 +--- a/drivers/net/ethernet/intel/i40e/i40e.h ++++ b/drivers/net/ethernet/intel/i40e/i40e.h +@@ -1286,4 +1286,18 @@ int i40e_add_del_cloud_filter(struct i40e_vsi *vsi, + int i40e_add_del_cloud_filter_big_buf(struct i40e_vsi *vsi, + struct i40e_cloud_filter *filter, + bool add); ++ ++/** ++ * i40e_is_tc_mqprio_enabled - check if TC MQPRIO is enabled on PF ++ * @pf: pointer to a pf. ++ * ++ * Check and return value of flag I40E_FLAG_TC_MQPRIO. ++ * ++ * Return: I40E_FLAG_TC_MQPRIO set state. ++ **/ ++static inline u32 i40e_is_tc_mqprio_enabled(struct i40e_pf *pf) ++{ ++ return pf->flags & I40E_FLAG_TC_MQPRIO; ++} ++ + #endif /* _I40E_H_ */ +diff --git a/drivers/net/ethernet/intel/i40e/i40e_ethtool.c b/drivers/net/ethernet/intel/i40e/i40e_ethtool.c +index 669ae53f4c728..8e770c5e181ea 100644 +--- a/drivers/net/ethernet/intel/i40e/i40e_ethtool.c ++++ b/drivers/net/ethernet/intel/i40e/i40e_ethtool.c +@@ -4921,7 +4921,7 @@ static int i40e_set_channels(struct net_device *dev, + /* We do not support setting channels via ethtool when TCs are + * configured through mqprio + */ +- if (pf->flags & I40E_FLAG_TC_MQPRIO) ++ if (i40e_is_tc_mqprio_enabled(pf)) + return -EINVAL; + + /* verify they are not requesting separate vectors */ +diff --git a/drivers/net/ethernet/intel/i40e/i40e_main.c b/drivers/net/ethernet/intel/i40e/i40e_main.c +index 536f9198bd47a..f373072dd3b30 100644 +--- a/drivers/net/ethernet/intel/i40e/i40e_main.c ++++ b/drivers/net/ethernet/intel/i40e/i40e_main.c +@@ -5320,7 +5320,7 @@ static u8 i40e_pf_get_num_tc(struct i40e_pf *pf) + u8 num_tc = 0; + struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config; + +- if (pf->flags & I40E_FLAG_TC_MQPRIO) ++ if (i40e_is_tc_mqprio_enabled(pf)) + return pf->vsi[pf->lan_vsi]->mqprio_qopt.qopt.num_tc; + + /* If neither MQPRIO nor DCB is enabled, then always use single TC */ +@@ -5352,7 +5352,7 @@ static u8 i40e_pf_get_num_tc(struct i40e_pf *pf) + **/ + static u8 i40e_pf_get_tc_map(struct i40e_pf *pf) + { +- if (pf->flags & I40E_FLAG_TC_MQPRIO) ++ if (i40e_is_tc_mqprio_enabled(pf)) + return i40e_mqprio_get_enabled_tc(pf); + + /* If neither MQPRIO nor DCB is enabled for this PF then just return +@@ -5449,7 +5449,7 @@ static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc, + int i; + + /* There is no need to reset BW when mqprio mode is on. */ +- if (pf->flags & I40E_FLAG_TC_MQPRIO) ++ if (i40e_is_tc_mqprio_enabled(pf)) + return 0; + if (!vsi->mqprio_qopt.qopt.hw && !(pf->flags & I40E_FLAG_DCB_ENABLED)) { + ret = i40e_set_bw_limit(vsi, vsi->seid, 0); +@@ -5521,7 +5521,7 @@ static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc) + vsi->tc_config.tc_info[i].qoffset); + } + +- if (pf->flags & I40E_FLAG_TC_MQPRIO) ++ if (i40e_is_tc_mqprio_enabled(pf)) + return; + + /* Assign UP2TC map for the VSI */ +@@ -5682,7 +5682,7 @@ static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc) + ctxt.vf_num = 0; + ctxt.uplink_seid = vsi->uplink_seid; + ctxt.info = vsi->info; +- if (vsi->back->flags & I40E_FLAG_TC_MQPRIO) { ++ if (i40e_is_tc_mqprio_enabled(pf)) { + ret = i40e_vsi_setup_queue_map_mqprio(vsi, &ctxt, enabled_tc); + if (ret) + goto out; +@@ -6406,7 +6406,7 @@ int i40e_create_queue_channel(struct i40e_vsi *vsi, + pf->flags |= I40E_FLAG_VEB_MODE_ENABLED; + + if (vsi->type == I40E_VSI_MAIN) { +- if (pf->flags & I40E_FLAG_TC_MQPRIO) ++ if (i40e_is_tc_mqprio_enabled(pf)) + i40e_do_reset(pf, I40E_PF_RESET_FLAG, true); + else + i40e_do_reset_safe(pf, I40E_PF_RESET_FLAG); +@@ -7800,7 +7800,7 @@ static void *i40e_fwd_add(struct net_device *netdev, struct net_device *vdev) + netdev_info(netdev, "Macvlans are not supported when DCB is enabled\n"); + return ERR_PTR(-EINVAL); + } +- if ((pf->flags & I40E_FLAG_TC_MQPRIO)) { ++ if (i40e_is_tc_mqprio_enabled(pf)) { + netdev_info(netdev, "Macvlans are not supported when HW TC offload is on\n"); + return ERR_PTR(-EINVAL); + } +@@ -8053,7 +8053,7 @@ static int i40e_setup_tc(struct net_device *netdev, void *type_data) + /* Quiesce VSI queues */ + i40e_quiesce_vsi(vsi); + +- if (!hw && !(pf->flags & I40E_FLAG_TC_MQPRIO)) ++ if (!hw && !i40e_is_tc_mqprio_enabled(pf)) + i40e_remove_queue_channels(vsi); + + /* Configure VSI for enabled TCs */ +@@ -8077,7 +8077,7 @@ static int i40e_setup_tc(struct net_device *netdev, void *type_data) + "Setup channel (id:%u) utilizing num_queues %d\n", + vsi->seid, vsi->tc_config.tc_info[0].qcount); + +- if (pf->flags & I40E_FLAG_TC_MQPRIO) { ++ if (i40e_is_tc_mqprio_enabled(pf)) { + if (vsi->mqprio_qopt.max_rate[0]) { + u64 max_tx_rate = vsi->mqprio_qopt.max_rate[0]; + +@@ -10731,7 +10731,7 @@ static void i40e_rebuild(struct i40e_pf *pf, bool reinit, bool lock_acquired) + * unless I40E_FLAG_TC_MQPRIO was enabled or DCB + * is not supported with new link speed + */ +- if (pf->flags & I40E_FLAG_TC_MQPRIO) { ++ if (i40e_is_tc_mqprio_enabled(pf)) { + i40e_aq_set_dcb_parameters(hw, false, NULL); + } else { + if (I40E_IS_X710TL_DEVICE(hw->device_id) && +-- +2.35.1 + diff --git a/queue-5.15/iommu-amd-use-full-64-bit-value-in-build_completion_.patch b/queue-5.15/iommu-amd-use-full-64-bit-value-in-build_completion_.patch new file mode 100644 index 00000000000..14308cc767b --- /dev/null +++ b/queue-5.15/iommu-amd-use-full-64-bit-value-in-build_completion_.patch @@ -0,0 +1,39 @@ +From 2ce5f1434eed47efbf8b24f3cb29a39463068c3a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 1 Aug 2022 19:22:29 +0000 +Subject: iommu/amd: use full 64-bit value in build_completion_wait() + +From: John Sperbeck + +[ Upstream commit 94a568ce32038d8ff9257004bb4632e60eb43a49 ] + +We started using a 64 bit completion value. Unfortunately, we only +stored the low 32-bits, so a very large completion value would never +be matched in iommu_completion_wait(). + +Fixes: c69d89aff393 ("iommu/amd: Use 4K page for completion wait write-back semaphore") +Signed-off-by: John Sperbeck +Link: https://lore.kernel.org/r/20220801192229.3358786-1-jsperbeck@google.com +Signed-off-by: Joerg Roedel +Signed-off-by: Sasha Levin +--- + drivers/iommu/amd/iommu.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c +index e23e70af718f1..7154fb551ddc9 100644 +--- a/drivers/iommu/amd/iommu.c ++++ b/drivers/iommu/amd/iommu.c +@@ -852,7 +852,8 @@ static void build_completion_wait(struct iommu_cmd *cmd, + memset(cmd, 0, sizeof(*cmd)); + cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK; + cmd->data[1] = upper_32_bits(paddr); +- cmd->data[2] = data; ++ cmd->data[2] = lower_32_bits(data); ++ cmd->data[3] = upper_32_bits(data); + CMD_SET_TYPE(cmd, CMD_COMPL_WAIT); + } + +-- +2.35.1 + diff --git a/queue-5.15/kbuild-disable-header-exports-for-uml-in-a-straightf.patch b/queue-5.15/kbuild-disable-header-exports-for-uml-in-a-straightf.patch new file mode 100644 index 00000000000..a570a4c910e --- /dev/null +++ b/queue-5.15/kbuild-disable-header-exports-for-uml-in-a-straightf.patch @@ -0,0 +1,42 @@ +From 351e75591442b8f2d1817c93c2c25cd753380f03 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 1 Sep 2022 10:12:52 +0900 +Subject: kbuild: disable header exports for UML in a straightforward way + +From: Masahiro Yamada + +[ Upstream commit 1b620d539ccc18a1aca1613d9ff078115a7891a1 ] + +Previously 'make ARCH=um headers' stopped because of missing +arch/um/include/uapi/asm/Kbuild. + +The error is not shown since commit ed102bf2afed ("um: Fix W=1 +missing-include-dirs warnings") added arch/um/include/uapi/asm/Kbuild. + +Hard-code the unsupported architecture, so it works like before. + +Fixes: ed102bf2afed ("um: Fix W=1 missing-include-dirs warnings") +Signed-off-by: Masahiro Yamada +Acked-by: Richard Weinberger +Signed-off-by: Sasha Levin +--- + Makefile | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/Makefile b/Makefile +index eca45b7be9c1e..32253ea989217 100644 +--- a/Makefile ++++ b/Makefile +@@ -1332,8 +1332,7 @@ hdr-inst := -f $(srctree)/scripts/Makefile.headersinst obj + + PHONY += headers + headers: $(version_h) scripts_unifdef uapi-asm-generic archheaders archscripts +- $(if $(wildcard $(srctree)/arch/$(SRCARCH)/include/uapi/asm/Kbuild),, \ +- $(error Headers not exportable for the $(SRCARCH) architecture)) ++ $(if $(filter um, $(SRCARCH)), $(error Headers not exportable for UML)) + $(Q)$(MAKE) $(hdr-inst)=include/uapi + $(Q)$(MAKE) $(hdr-inst)=arch/$(SRCARCH)/include/uapi + +-- +2.35.1 + diff --git a/queue-5.15/mips-loongson32-ls1c-fix-hang-during-startup.patch b/queue-5.15/mips-loongson32-ls1c-fix-hang-during-startup.patch new file mode 100644 index 00000000000..e54a8a676f3 --- /dev/null +++ b/queue-5.15/mips-loongson32-ls1c-fix-hang-during-startup.patch @@ -0,0 +1,37 @@ +From a4a8cc45b546c225e6cd1138eab939100d625bd3 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 23 Aug 2022 19:17:25 +0800 +Subject: MIPS: loongson32: ls1c: Fix hang during startup + +From: Yang Ling + +[ Upstream commit 35508d2424097f9b6a1a17aac94f702767035616 ] + +The RTCCTRL reg of LS1C is obselete. +Writing this reg will cause system hang. + +Fixes: 60219c563c9b6 ("MIPS: Add RTC support for Loongson1C board") +Signed-off-by: Yang Ling +Tested-by: Keguang Zhang +Acked-by: Keguang Zhang +Signed-off-by: Thomas Bogendoerfer +Signed-off-by: Sasha Levin +--- + arch/mips/loongson32/ls1c/board.c | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/arch/mips/loongson32/ls1c/board.c b/arch/mips/loongson32/ls1c/board.c +index e9de6da0ce51f..9dcfe9de55b0a 100644 +--- a/arch/mips/loongson32/ls1c/board.c ++++ b/arch/mips/loongson32/ls1c/board.c +@@ -15,7 +15,6 @@ static struct platform_device *ls1c_platform_devices[] __initdata = { + static int __init ls1c_platform_init(void) + { + ls1x_serial_set_uartclk(&ls1x_uart_pdev); +- ls1x_rtc_set_extclk(&ls1x_rtc_pdev); + + return platform_add_devices(ls1c_platform_devices, + ARRAY_SIZE(ls1c_platform_devices)); +-- +2.35.1 + diff --git a/queue-5.15/s390-boot-fix-absolute-zero-lowcore-corruption-on-bo.patch b/queue-5.15/s390-boot-fix-absolute-zero-lowcore-corruption-on-bo.patch new file mode 100644 index 00000000000..967de3bb0f1 --- /dev/null +++ b/queue-5.15/s390-boot-fix-absolute-zero-lowcore-corruption-on-bo.patch @@ -0,0 +1,54 @@ +From d2881b0d5e69c2dd0bdcfa6656c0f25996c6de36 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 13 Aug 2022 19:45:21 +0200 +Subject: s390/boot: fix absolute zero lowcore corruption on boot + +From: Alexander Gordeev + +[ Upstream commit 12dd19c159659ec9050f45dc8a2ff3c3917f4be3 ] + +Crash dump always starts on CPU0. In case CPU0 is offline the +prefix page is not installed and the absolute zero lowcore is +used. However, struct lowcore::mcesad is never assigned and +stays zero. That leads to __machine_kdump() -> save_vx_regs() +call silently stores vector registers to the absolute lowcore +at 0x11b0 offset. + +Fixes: a62bc0739253 ("s390/kdump: add support for vector extension") +Reviewed-by: Heiko Carstens +Signed-off-by: Alexander Gordeev +Signed-off-by: Vasily Gorbik +Signed-off-by: Sasha Levin +--- + arch/s390/kernel/nmi.c | 2 +- + arch/s390/kernel/setup.c | 1 + + 2 files changed, 2 insertions(+), 1 deletion(-) + +diff --git a/arch/s390/kernel/nmi.c b/arch/s390/kernel/nmi.c +index a50f2ff1b00e8..383b4799b6dd3 100644 +--- a/arch/s390/kernel/nmi.c ++++ b/arch/s390/kernel/nmi.c +@@ -62,7 +62,7 @@ static inline unsigned long nmi_get_mcesa_size(void) + * The structure is required for machine check happening early in + * the boot process. + */ +-static struct mcesa boot_mcesa __initdata __aligned(MCESA_MAX_SIZE); ++static struct mcesa boot_mcesa __aligned(MCESA_MAX_SIZE); + + void __init nmi_alloc_boot_cpu(struct lowcore *lc) + { +diff --git a/arch/s390/kernel/setup.c b/arch/s390/kernel/setup.c +index 6b1a8697fae8d..4dfe37b068898 100644 +--- a/arch/s390/kernel/setup.c ++++ b/arch/s390/kernel/setup.c +@@ -484,6 +484,7 @@ static void __init setup_lowcore_dat_off(void) + put_abs_lowcore(restart_data, lc->restart_data); + put_abs_lowcore(restart_source, lc->restart_source); + put_abs_lowcore(restart_psw, lc->restart_psw); ++ put_abs_lowcore(mcesad, lc->mcesad); + + lc->spinlock_lockval = arch_spin_lockval(0); + lc->spinlock_index = 0; +-- +2.35.1 + diff --git a/queue-5.15/series b/queue-5.15/series index 38e5ce6f0d4..d3b140993ad 100644 --- a/queue-5.15/series +++ b/queue-5.15/series @@ -100,3 +100,15 @@ perf-script-fix-cannot-print-iregs-field-for-hybrid-.patch hwmon-tps23861-fix-byte-order-in-resistance-register.patch asoc-mchp-spdiftx-remove-references-to-mchp_i2s_caps.patch asoc-mchp-spdiftx-fix-clang-wbitfield-constant-conversion.patch +mips-loongson32-ls1c-fix-hang-during-startup.patch +kbuild-disable-header-exports-for-uml-in-a-straightf.patch +i40e-refactor-tc-mqprio-checks.patch +i40e-fix-adq-rate-limiting-for-pf.patch +swiotlb-avoid-potential-left-shift-overflow.patch +iommu-amd-use-full-64-bit-value-in-build_completion_.patch +s390-boot-fix-absolute-zero-lowcore-corruption-on-bo.patch +hwmon-mr75203-fix-vm-sensor-allocation-when-intel-vm.patch +hwmon-mr75203-update-pvt-v_num-and-vm_num-to-the-act.patch +hwmon-mr75203-fix-voltage-equation-for-negative-sour.patch +hwmon-mr75203-fix-multi-channel-voltage-reading.patch +hwmon-mr75203-enable-polling-for-all-vm-channels.patch diff --git a/queue-5.15/swiotlb-avoid-potential-left-shift-overflow.patch b/queue-5.15/swiotlb-avoid-potential-left-shift-overflow.patch new file mode 100644 index 00000000000..2a2491994e8 --- /dev/null +++ b/queue-5.15/swiotlb-avoid-potential-left-shift-overflow.patch @@ -0,0 +1,44 @@ +From aa441acc6868fcd7116b66024b9c11c9bd054dcd Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 19 Aug 2022 16:45:37 +0800 +Subject: swiotlb: avoid potential left shift overflow + +From: Chao Gao + +[ Upstream commit 3f0461613ebcdc8c4073e235053d06d5aa58750f ] + +The second operand passed to slot_addr() is declared as int or unsigned int +in all call sites. The left-shift to get the offset of a slot can overflow +if swiotlb size is larger than 4G. + +Convert the macro to an inline function and declare the second argument as +phys_addr_t to avoid the potential overflow. + +Fixes: 26a7e094783d ("swiotlb: refactor swiotlb_tbl_map_single") +Signed-off-by: Chao Gao +Reviewed-by: Dongli Zhang +Signed-off-by: Christoph Hellwig +Signed-off-by: Sasha Levin +--- + kernel/dma/swiotlb.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +diff --git a/kernel/dma/swiotlb.c b/kernel/dma/swiotlb.c +index e62fb7a4da694..018f140aaaf4e 100644 +--- a/kernel/dma/swiotlb.c ++++ b/kernel/dma/swiotlb.c +@@ -435,7 +435,10 @@ static void swiotlb_bounce(struct device *dev, phys_addr_t tlb_addr, size_t size + } + } + +-#define slot_addr(start, idx) ((start) + ((idx) << IO_TLB_SHIFT)) ++static inline phys_addr_t slot_addr(phys_addr_t start, phys_addr_t idx) ++{ ++ return start + (idx << IO_TLB_SHIFT); ++} + + /* + * Carefully handle integer overflow which can occur when boundary_mask == ~0UL. +-- +2.35.1 +