From: Wangao Wang Date: Fri, 29 May 2026 07:34:58 +0000 (+0800) Subject: media: dt-bindings: qcom,sm8550-iris: Add X1P42100 compatible X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=96789be88f987d733a07b37279d4ebc8efd6207a;p=thirdparty%2Fkernel%2Fstable.git media: dt-bindings: qcom,sm8550-iris: Add X1P42100 compatible Document the new compatible string "qcom,x1p42100-iris". Unlike SM8550 where the BSE (Bitstream Engine) is clocked implicitly via vcodec0_core, x1p42100 exposes a dedicated BSE clock vcodec0_bse that requires explicit enable/disable and frequency configuration. The SM8550 driver has no knowledge of this clock and therefore cannot operate x1p42100 hardware correctly. Reviewed-by: Bryan O'Donoghue Reviewed-by: Krzysztof Kozlowski Signed-off-by: Wangao Wang Signed-off-by: Bryan O'Donoghue --- diff --git a/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml b/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml index 9c4b760508b5..0400ca1bff05 100644 --- a/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml @@ -26,6 +26,7 @@ properties: - qcom,qcs8300-iris - qcom,sm8550-iris - qcom,sm8650-iris + - qcom,x1p42100-iris reg: maxItems: 1 @@ -41,13 +42,16 @@ properties: - const: mmcx clocks: - maxItems: 3 + minItems: 3 + maxItems: 4 clock-names: + minItems: 3 items: - const: iface - const: core - const: vcodec0_core + - const: vcodec0_bse firmware-name: maxItems: 1 @@ -115,6 +119,23 @@ allOf: maxItems: 1 reset-names: maxItems: 1 + - if: + properties: + compatible: + enum: + - qcom,x1p42100-iris + then: + properties: + clocks: + minItems: 4 + clock-names: + minItems: 4 + else: + properties: + clocks: + maxItems: 3 + clock-names: + maxItems: 3 unevaluatedProperties: false