From: Peter Bergner Date: Mon, 1 Dec 2025 23:03:44 +0000 (-0700) Subject: [PATCH][PR target/122942] RISC-V: Add zifencei extension to the rva23s64 and rvb23s64... X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=976be4e0148b614fccb60c85e5b3bc96e0bb26b6;p=thirdparty%2Fgcc.git [PATCH][PR target/122942] RISC-V: Add zifencei extension to the rva23s64 and rvb23s64 profiles [PR122942] While verifying our Ascalon extensions list was complete (it isn't, follow-on patch coming), I noticed that the rva23s64 and rvb23s64 profiles were missing the mandatory zifencei extension, hence the following patch. This was bootstrapped and regtested with no regressions. Ok for trunk? Peter The RVA23S64 and RVB23S64 profiles both state that zifencei is a mandatory extension. Add it to both profiles. gcc/ PR target/122942 * config/riscv/riscv-profiles.def (rva23s64): Add zifencei. (rvb23s64): Likewise. --- diff --git a/gcc/config/riscv/riscv-profiles.def b/gcc/config/riscv/riscv-profiles.def index 741c4719b37..ea1c235a22c 100644 --- a/gcc/config/riscv/riscv-profiles.def +++ b/gcc/config/riscv/riscv-profiles.def @@ -61,7 +61,7 @@ RISCV_PROFILE("rva23s64", "rv64imafdcbv_zicsr_zicntr_zihpm_ziccif_ziccrse" "_zicbom_zicbop_zicboz_zfhmin_zkt_zvfhmin_zvbb_zvkt_zihintntl" "_zicond_zimop_zcmop_zcb_zfa_zawrs_svbare_svade_ssccptr" "_sstvecd_sstvala_sscounterenw_svpbmt_svinval_svnapot_sstc" - "_sscofpmf_ssnpm_ssu64xl_sha_supm") + "_sscofpmf_ssnpm_ssu64xl_sha_supm_zifencei") /* RVB23 contains all mandatory base ISA for RVA22U64 and the new extension 'zihintntl,zicond,zimop,zcmop,zfa,zawrs' as mandatory extensions. */ @@ -77,6 +77,6 @@ RISCV_PROFILE("rvb23s64", "rv64imafdcb_zicsr_zicntr_zihpm_ziccif_ziccrse" "_zicbom_zicbop_zicboz_zfhmin_zkt_zvfhmin_zvbb_zvkt" "_zihintntl_zicond_zimop_zcmop_zcb_zfa_zawrs_svbare_svade" "_ssccptr_sstvecd_sstvala_sscounterenw_svpbmt_svinval_svnapot" - "_sstc_sscofpmf_ssu64xl_supm") + "_sstc_sscofpmf_ssu64xl_supm_zifencei") #undef RISCV_PROFILE