From: Lorenzo Bianconi Date: Fri, 1 May 2026 07:49:11 +0000 (+0200) Subject: net: airoha: Introduce airoha_fe_get()/airoha_qdma_get() register read helpers X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=98e490930de3af9afa0bbb2d1d79d6d5b5513012;p=thirdparty%2Fkernel%2Flinux.git net: airoha: Introduce airoha_fe_get()/airoha_qdma_get() register read helpers Add airoha_fe_get() and airoha_qdma_get() as utility routines for reading a masked field from a specified register. This is a non-functional refactor, no logical changes are introduced to the existing codebase. Signed-off-by: Lorenzo Bianconi Link: https://patch.msgid.link/20260501-airoha_fe_get-airoha_qdma_get-v3-1-126c6f647ccb@kernel.org Signed-off-by: Jakub Kicinski --- diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c index e9e1645e8f9b1..4222de6878d28 100644 --- a/drivers/net/ethernet/airoha/airoha_eth.c +++ b/drivers/net/ethernet/airoha/airoha_eth.c @@ -201,15 +201,13 @@ static void airoha_fe_vip_setup(struct airoha_eth *eth) static u32 airoha_fe_get_pse_queue_rsv_pages(struct airoha_eth *eth, u32 port, u32 queue) { - u32 val; - airoha_fe_rmw(eth, REG_FE_PSE_QUEUE_CFG_WR, PSE_CFG_PORT_ID_MASK | PSE_CFG_QUEUE_ID_MASK, FIELD_PREP(PSE_CFG_PORT_ID_MASK, port) | FIELD_PREP(PSE_CFG_QUEUE_ID_MASK, queue)); - val = airoha_fe_rr(eth, REG_FE_PSE_QUEUE_CFG_VAL); - return FIELD_GET(PSE_CFG_OQ_RSV_MASK, val); + return airoha_fe_get(eth, REG_FE_PSE_QUEUE_CFG_VAL, + PSE_CFG_OQ_RSV_MASK); } static void airoha_fe_set_pse_queue_rsv_pages(struct airoha_eth *eth, @@ -227,9 +225,7 @@ static void airoha_fe_set_pse_queue_rsv_pages(struct airoha_eth *eth, static u32 airoha_fe_get_pse_all_rsv(struct airoha_eth *eth) { - u32 val = airoha_fe_rr(eth, REG_FE_PSE_BUF_SET); - - return FIELD_GET(PSE_ALLRSV_MASK, val); + return airoha_fe_get(eth, REG_FE_PSE_BUF_SET, PSE_ALLRSV_MASK); } static int airoha_fe_set_pse_oq_rsv(struct airoha_eth *eth, @@ -247,8 +243,7 @@ static int airoha_fe_set_pse_oq_rsv(struct airoha_eth *eth, FIELD_PREP(PSE_ALLRSV_MASK, all_rsv)); /* modify hthd */ - tmp = airoha_fe_rr(eth, PSE_FQ_CFG); - fq_limit = FIELD_GET(PSE_FQ_LIMIT_MASK, tmp); + fq_limit = airoha_fe_get(eth, PSE_FQ_CFG, PSE_FQ_LIMIT_MASK); tmp = fq_limit - all_rsv - 0x20; airoha_fe_rmw(eth, REG_PSE_SHARE_USED_THD, PSE_SHARE_USED_HTHD_MASK, diff --git a/drivers/net/ethernet/airoha/airoha_eth.h b/drivers/net/ethernet/airoha/airoha_eth.h index 717e4a7c59dd2..58530d096de76 100644 --- a/drivers/net/ethernet/airoha/airoha_eth.h +++ b/drivers/net/ethernet/airoha/airoha_eth.h @@ -619,6 +619,8 @@ u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val); airoha_rmw((eth)->fe_regs, (offset), 0, (val)) #define airoha_fe_clear(eth, offset, val) \ airoha_rmw((eth)->fe_regs, (offset), (val), 0) +#define airoha_fe_get(eth, offset, mask) \ + FIELD_GET((mask), airoha_fe_rr((eth), (offset))) #define airoha_qdma_rr(qdma, offset) \ airoha_rr((qdma)->regs, (offset)) @@ -630,6 +632,8 @@ u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val); airoha_rmw((qdma)->regs, (offset), 0, (val)) #define airoha_qdma_clear(qdma, offset, val) \ airoha_rmw((qdma)->regs, (offset), (val), 0) +#define airoha_qdma_get(qdma, offset, mask) \ + FIELD_GET((mask), airoha_qdma_rr((qdma), (offset))) static inline u16 airoha_qdma_get_txq(struct airoha_qdma *qdma, u16 qid) { diff --git a/drivers/net/ethernet/airoha/airoha_ppe.c b/drivers/net/ethernet/airoha/airoha_ppe.c index e833c50ac35fe..26da519236bfc 100644 --- a/drivers/net/ethernet/airoha/airoha_ppe.c +++ b/drivers/net/ethernet/airoha/airoha_ppe.c @@ -80,9 +80,8 @@ bool airoha_ppe_is_enabled(struct airoha_eth *eth, int index) static u32 airoha_ppe_get_timestamp(struct airoha_ppe *ppe) { - u16 timestamp = airoha_fe_rr(ppe->eth, REG_FE_FOE_TS); - - return FIELD_GET(AIROHA_FOE_IB1_BIND_TIMESTAMP, timestamp); + return airoha_fe_get(ppe->eth, REG_FE_FOE_TS, + AIROHA_FOE_IB1_BIND_TIMESTAMP); } void airoha_ppe_set_cpu_port(struct airoha_gdm_port *port, u8 ppe_id, u8 fport)